st40reg.h

采用ST20 CPU的机顶盒的烧写程序

/*
 * Copyright (C) STMicroelectronics Ltd. 2002, 2003.
 *
 * All rights reserved.
 */

#ifndef __ST40REG_H
#define __ST40REG_H

#include "sh4regtype.h"

/*----------------------------------------------------------------------------*/

#include "sh4reg.h"

/*----------------------------------------------------------------------------*/

/*
 * ST40 control registers
 */

/* Clock Pulse Generator control registers (all ST40 variants) */
#define ST40_CPG_FRQCR SH4_WORD_REG(ST40_CPG_REGS_BASE + 0x00)
#define ST40_CPG_STBCR SH4_BYTE_REG(ST40_CPG_REGS_BASE + 0x04)
#define ST40_CPG_WTCNT SH4_WORD_REG(ST40_CPG_REGS_BASE + 0x08)
#define ST40_CPG_WTCNT_R SH4_BYTE_REG(ST40_CPG_REGS_BASE + 0x08)
#define ST40_CPG_WTCSR SH4_WORD_REG(ST40_CPG_REGS_BASE + 0x0c)
#define ST40_CPG_WTCSR_R SH4_BYTE_REG(ST40_CPG_REGS_BASE + 0x0c)
#define ST40_CPG_STBCR2 SH4_BYTE_REG(ST40_CPG_REGS_BASE + 0x10)
#define ST40_CPG_FRQCR2 SH4_WORD_REG(ST40_CPG_REGS_BASE + 0xc0)

/* Interrupt controller registers (all ST40 variants) */
#define ST40_INTC_ICR SH4_WORD_REG(ST40_INTC_REGS_BASE + 0x00)
#define ST40_INTC_IPRA SH4_WORD_REG(ST40_INTC_REGS_BASE + 0x04)
#define ST40_INTC_IPRB SH4_WORD_REG(ST40_INTC_REGS_BASE + 0x08)
#define ST40_INTC_IPRC SH4_WORD_REG(ST40_INTC_REGS_BASE + 0x0c)
#define ST40_INTC_IPRD SH4_WORD_REG(ST40_INTC_REGS_BASE + 0x10)

/* Interrupt Controller control registers (all ST40 variants) */
#define ST40_INTC2_INTPRI00 SH4_DWORD_REG(ST40_INTC2_REGS_BASE + 0x00)
#define ST40_INTC2_INTPRI04 SH4_DWORD_REG(ST40_INTC2_REGS_BASE + 0x04)
#define ST40_INTC2_INTPRI08 SH4_DWORD_REG(ST40_INTC2_REGS_BASE + 0x08)
#define ST40_INTC2_INTREQ00 SH4_DWORD_REG(ST40_INTC2_REGS_BASE + 0x20)
#define ST40_INTC2_INTREQ04 SH4_DWORD_REG(ST40_INTC2_REGS_BASE + 0x24)
#define ST40_INTC2_INTREQ08 SH4_DWORD_REG(ST40_INTC2_REGS_BASE + 0x28)
#define ST40_INTC2_INTMSK00 SH4_DWORD_REG(ST40_INTC2_REGS_BASE + 0x40)
#define ST40_INTC2_INTMSK04 SH4_DWORD_REG(ST40_INTC2_REGS_BASE + 0x44)
#define ST40_INTC2_INTMSK08 SH4_DWORD_REG(ST40_INTC2_REGS_BASE + 0x48)
#define ST40_INTC2_INTMSKCLR00 SH4_DWORD_REG(ST40_INTC2_REGS_BASE + 0x60)
#define ST40_INTC2_INTMSKCLR04 SH4_DWORD_REG(ST40_INTC2_REGS_BASE + 0x64)
#define ST40_INTC2_INTMSKCLR08 SH4_DWORD_REG(ST40_INTC2_REGS_BASE + 0x68)
#define ST40_INTC2_INTC2MODE SH4_DWORD_REG(ST40_INTC2_REGS_BASE + 0x80)

/* Interrupt Level Controller control registers (all ST40 variants) */
#define ST40_ILC_INPUT_INTERRUPT(n) SH4_DWORD_REG(ST40_ILC_REGS_BASE + (0x0080 + ((n) * 4)))
#define ST40_ILC_STATUS(n) SH4_DWORD_REG(ST40_ILC_REGS_BASE + (0x0200 + ((n) * 4)))
#define ST40_ILC_CLEAR_STATUS(n) SH4_DWORD_REG(ST40_ILC_REGS_BASE + (0x0280 + ((n) * 4)))
#define ST40_ILC_ENABLE(n) SH4_DWORD_REG(ST40_ILC_REGS_BASE + (0x0400 + ((n) * 4)))
#define ST40_ILC_CLEAR_ENABLE(n) SH4_DWORD_REG(ST40_ILC_REGS_BASE + (0x0480 + ((n) * 4)))
#define ST40_ILC_SET_ENABLE(n) SH4_DWORD_REG(ST40_ILC_REGS_BASE + (0x0500 + ((n) * 4)))
#define ST40_ILC_WAKEUP_ENABLE(n) SH4_DWORD_REG(ST40_ILC_REGS_BASE + (0x0600 + ((n) * 4)))
#define ST40_ILC_WAKEUP_ACTIVE_LEVEL(n) SH4_DWORD_REG(ST40_ILC_REGS_BASE + (0x0680 + ((n) * 4)))

/* Serial Communication Interfaces control registers (all ST40 variants) */
#define ST40_SCIF_SCSMR(n) SH4_WORD_REG(ST40_SCIF##n##_REGS_BASE + 0x00)
#define ST40_SCIF_SCBRR(n) SH4_BYTE_REG(ST40_SCIF##n##_REGS_BASE + 0x04)
#define ST40_SCIF_SCSCR(n) SH4_WORD_REG(ST40_SCIF##n##_REGS_BASE + 0x08)
#define ST40_SCIF_SCFTDR(n) SH4_BYTE_REG(ST40_SCIF##n##_REGS_BASE + 0x0c)
#define ST40_SCIF_SCFSR(n) SH4_WORD_REG(ST40_SCIF##n##_REGS_BASE + 0x10)
#define ST40_SCIF_SCFRDR(n) SH4_BYTE_REG(ST40_SCIF##n##_REGS_BASE + 0x14)
#define ST40_SCIF_SCFCR(n) SH4_WORD_REG(ST40_SCIF##n##_REGS_BASE + 0x18)
#define ST40_SCIF_SCFDR(n) SH4_WORD_REG(ST40_SCIF##n##_REGS_BASE + 0x1c)
#define ST40_SCIF_SCSPTR(n) SH4_WORD_REG(ST40_SCIF##n##_REGS_BASE + 0x20)
#define ST40_SCIF_SCLSR(n) SH4_WORD_REG(ST40_SCIF##n##_REGS_BASE + 0x24)

/* Clock Generator control registers (all ST40 variants) */
#define ST40_CLOCKGEN_PLL1CR1(n) SH4_DWORD_REG(ST40_CLOCKGEN##n##_REGS_BASE + 0x00)
#define ST40_CLOCKGEN_PLL1CR2(n) SH4_DWORD_REG(ST40_CLOCKGEN##n##_REGS_BASE + 0x08)
#define ST40_CLOCKGEN_PLL2CR(n) SH4_DWORD_REG(ST40_CLOCKGEN##n##_REGS_BASE + 0x10)
#define ST40_CLOCKGEN_STBREQCR(n) SH4_DWORD_REG(ST40_CLOCKGEN##n##_REGS_BASE + 0x18)
#define ST40_CLOCKGEN_STBREQCR_SET(n) SH4_DWORD_REG(ST40_CLOCKGEN##n##_REGS_BASE + 0x20)
#define ST40_CLOCKGEN_STBREQCR_CLR(n) SH4_DWORD_REG(ST40_CLOCKGEN##n##_REGS_BASE + 0x28)
#define ST40_CLOCKGEN_STBACKCR(n) SH4_DWORD_REG(ST40_CLOCKGEN##n##_REGS_BASE + 0x30)
#define ST40_CLOCKGEN_CLK4CR(n) SH4_DWORD_REG(ST40_CLOCKGEN##n##_REGS_BASE + 0x38)
#define ST40_CLOCKGEN_CPG_BYPASS(n) SH4_DWORD_REG(ST40_CLOCKGEN##n##_REGS_BASE + 0x40)
#define ST40_CLOCKGEN_PLL2_MUXCR(n) SH4_DWORD_REG(ST40_CLOCKGEN##n##_REGS_BASE + 0x48)
#define ST40_CLOCKGEN_CLK1CR(n) SH4_DWORD_REG(ST40_CLOCKGEN##n##_REGS_BASE + 0x50)
#define ST40_CLOCKGEN_CLK2CR(n) SH4_DWORD_REG(ST40_CLOCKGEN##n##_REGS_BASE + 0x58)
#define ST40_CLOCKGEN_CLK3CR(n) SH4_DWORD_REG(ST40_CLOCKGEN##n##_REGS_BASE + 0x60)
#define ST40_CLOCKGEN_CLK_SELCR(n) SH4_DWORD_REG(ST40_CLOCKGEN##n##_REGS_BASE + 0x68)

#define ST40_CLOCKGEN_CLK_RATIO(n) ST40_CLOCKGEN_PLL2_MUXCR(n)
#define ST40_CLOCKGEN_CLKDDRCR(n) ST40_CLOCKGEN_CLK_SELCR(n)

/* Direct Memeory Access Controller control registers (all ST40 variants) */
#define ST40_DMAC_CHAN0_IDENTITY SH4_DWORD_REG((ST40_DMAC_REGS_BASE + 0x100) + 0x00)
#define ST40_DMAC_CHAN0_ENABLE SH4_DWORD_REG((ST40_DMAC_REGS_BASE + 0x100) + 0x08)
#define ST40_DMAC_CHAN0_DISABLE SH4_DWORD_REG((ST40_DMAC_REGS_BASE + 0x100) + 0x10)
#define ST40_DMAC_CHAN0_STATUS SH4_DWORD_REG((ST40_DMAC_REGS_BASE + 0x100) + 0x18)
#define ST40_DMAC_CHAN0_ACTION SH4_DWORD_REG((ST40_DMAC_REGS_BASE + 0x100) + 0x20)
#define ST40_DMAC_CHAN0_POINTER SH4_DWORD_REG((ST40_DMAC_REGS_BASE + 0x100) + 0x28)
#define ST40_DMAC_CHAN0_SUBBASE SH4_DWORD_REG((ST40_DMAC_REGS_BASE + 0x100) + 0x30)
#define ST40_DMAC_CHAN0_SUBENABLE SH4_DWORD_REG((ST40_DMAC_REGS_BASE + 0x100) + 0x38)
#define ST40_DMAC_CHAN0_SUBDISABLE SH4_DWORD_REG((ST40_DMAC_REGS_BASE + 0x100) + 0x40)
#define ST40_DMAC_CHAN0_SUBINT_ENB SH4_DWORD_REG((ST40_DMAC_REGS_BASE + 0x100) + 0x48)
#define ST40_DMAC_CHAN0_SUBINT_DIS SH4_DWORD_REG((ST40_DMAC_REGS_BASE + 0x100) + 0x50)
#define ST40_DMAC_CHAN0_SUBINT_STAT SH4_DWORD_REG((ST40_DMAC_REGS_BASE + 0x100) + 0x58)
#define ST40_DMAC_CHAN0_SUNINT_ACT SH4_DWORD_REG((ST40_DMAC_REGS_BASE + 0x100) + 0x60)
#define ST40_DMAC_CHAN0_CONTROL SH4_DWORD_REG((ST40_DMAC_REGS_BASE + 0x100) + 0x80)
#define ST40_DMAC_CHAN0_COUNT SH4_DWORD_REG((ST40_DMAC_REGS_BASE + 0x100) + 0x88)
#define ST40_DMAC_CHAN0_SAR SH4_DWORD_REG((ST40_DMAC_REGS_BASE + 0x100) + 0x90)
#define ST40_DMAC_CHAN0_DAR SH4_DWORD_REG((ST40_DMAC_REGS_BASE + 0x100) + 0x98)

#define ST40_DMAC_CHANX_IDENTITY(n) SH4_DWORD_REG((ST40_DMAC_REGS_BASE + (n)) + 0x00)
#define ST40_DMAC_CHANX_ENABLE(n) SH4_DWORD_REG((ST40_DMAC_REGS_BASE + (n)) + 0x08)
#define ST40_DMAC_CHANX_DISABLE(n) SH4_DWORD_REG((ST40_DMAC_REGS_BASE + (n)) + 0x10)
#define ST40_DMAC_CHANX_STATUS(n) SH4_DWORD_REG((ST40_DMAC_REGS_BASE + (n)) + 0x18)
#define ST40_DMAC_CHANX_ACTION(n) SH4_DWORD_REG((ST40_DMAC_REGS_BASE + (n)) + 0x20)
#define ST40_DMAC_CHANX_POINTER(n) SH4_DWORD_REG((ST40_DMAC_REGS_BASE + (n)) + 0x28)
#define ST40_DMAC_CHANX_REQUEST(n) SH4_DWORD_REG((ST40_DMAC_REGS_BASE + (n)) + 0x30)
#define ST40_DMAC_CHANX_CONTROL(n) SH4_DWORD_REG((ST40_DMAC_REGS_BASE + (n)) + 0x80)
#define ST40_DMAC_CHANX_COUNT(n) SH4_DWORD_REG((ST40_DMAC_REGS_BASE + (n)) + 0x88)
#define ST40_DMAC_CHANX_SAR(n) SH4_DWORD_REG((ST40_DMAC_REGS_BASE + (n)) + 0x90)
#define ST40_DMAC_CHANX_DAR(n) SH4_DWORD_REG((ST40_DMAC_REGS_BASE + (n)) + 0x98)
#define ST40_DMAC_CHANX_NEXT_PTR(n) SH4_DWORD_REG((ST40_DMAC_REGS_BASE + (n)) + 0xa0)
#define ST40_DMAC_CHANX_SRC_LENGTH(n) SH4_DWORD_REG((ST40_DMAC_REGS_BASE + (n)) + 0xa8)
#define ST40_DMAC_CHANX_SRC_STRIDE(n) SH4_DWORD_REG((ST40_DMAC_REGS_BASE + (n)) + 0xb0)
#define ST40_DMAC_CHANX_DST_LENGTH(n) SH4_DWORD_REG((ST40_DMAC_REGS_BASE + (n)) + 0xb8)
#define ST40_DMAC_CHANX_DST_STRIDE(n) SH4_DWORD_REG((ST40_DMAC_REGS_BASE + (n)) + 0xc0)

#define ST40_DMAC_CHAN1_IDENTITY ST40_DMAC_CHANX_IDENTITY(0x200)
#define ST40_DMAC_CHAN1_ENABLE ST40_DMAC_CHANX_ENABLE(0x200)
#define ST40_DMAC_CHAN1_DISABLE ST40_DMAC_CHANX_DISABLE(0x200)
#define ST40_DMAC_CHAN1_STATUS ST40_DMAC_CHANX_STATUS(0x200)
#define ST40_DMAC_CHAN1_ACTION ST40_DMAC_CHANX_ACTION(0x200)
#define ST40_DMAC_CHAN1_POINTER ST40_DMAC_CHANX_POINTER(0x200)
#define ST40_DMAC_CHAN1_REQUEST ST40_DMAC_CHANX_REQUEST(0x200)
#define ST40_DMAC_CHAN1_CONTROL ST40_DMAC_CHANX_CONTROL(0x200)
#define ST40_DMAC_CHAN1_COUNT ST40_DMAC_CHANX_COUNT(0x200)
#define ST40_DMAC_CHAN1_SAR ST40_DMAC_CHANX_SAR(0x200)
#define ST40_DMAC_CHAN1_DAR ST40_DMAC_CHANX_DAR(0x200)
#define ST40_DMAC_CHAN1_NEXT_PTR ST40_DMAC_CHANX_NEXT_PTR(0x200)
#define ST40_DMAC_CHAN1_SRC_LENGTH ST40_DMAC_CHANX_SRC_LENGTH(0x200)
#define ST40_DMAC_CHAN1_SRC_STRIDE ST40_DMAC_CHANX_SRC_STRIDE(0x200)
#define ST40_DMAC_CHAN1_DST_LENGTH ST40_DMAC_CHANX_DST_LENGTH(0x200)
#define ST40_DMAC_CHAN1_DST_STRIDE ST40_DMAC_CHANX_DST_STRIDE(0x200)

#define ST40_DMAC_CHAN2_IDENTITY ST40_DMAC_CHANX_IDENTITY(0x300)
#define ST40_DMAC_CHAN2_ENABLE ST40_DMAC_CHANX_ENABLE(0x300)
#define ST40_DMAC_CHAN2_DISABLE ST40_DMAC_CHANX_DISABLE(0x300)
#define ST40_DMAC_CHAN2_STATUS ST40_DMAC_CHANX_STATUS(0x300)
#define ST40_DMAC_CHAN2_ACTION ST40_DMAC_CHANX_ACTION(0x300)
#define ST40_DMAC_CHAN2_POINTER ST40_DMAC_CHANX_POINTER(0x300)
#define ST40_DMAC_CHAN2_REQUEST ST40_DMAC_CHANX_REQUEST(0x300)
#define ST40_DMAC_CHAN2_CONTROL ST40_DMAC_CHANX_CONTROL(0x300)
#define ST40_DMAC_CHAN2_COUNT ST40_DMAC_CHANX_COUNT(0x300)
#define ST40_DMAC_CHAN2_SAR ST40_DMAC_CHANX_SAR(0x300)
#define ST40_DMAC_CHAN2_DAR ST40_DMAC_CHANX_DAR(0x300)
#define ST40_DMAC_CHAN2_NEXT_PTR ST40_DMAC_CHANX_NEXT_PTR(0x300)
#define ST40_DMAC_CHAN2_SRC_LENGTH ST40_DMAC_CHANX_SRC_LENGTH(0x300)
#define ST40_DMAC_CHAN2_SRC_STRIDE ST40_DMAC_CHANX_SRC_STRIDE(0x300)
#define ST40_DMAC_CHAN2_DST_LENGTH ST40_DMAC_CHANX_DST_LENGTH(0x300)
#define ST40_DMAC_CHAN2_DST_STRIDE ST40_DMAC_CHANX_DST_STRIDE(0x300)

#define ST40_DMAC_CHAN3_IDENTITY ST40_DMAC_CHANX_IDENTITY(0x400)
#define ST40_DMAC_CHAN3_ENABLE ST40_DMAC_CHANX_ENABLE(0x400)
#define ST40_DMAC_CHAN3_DISABLE ST40_DMAC_CHANX_DISABLE(0x400)
#define ST40_DMAC_CHAN3_STATUS ST40_DMAC_CHANX_STATUS(0x400)
#define ST40_DMAC_CHAN3_ACTION ST40_DMAC_CHANX_ACTION(0x400)
#define ST40_DMAC_CHAN3_POINTER ST40_DMAC_CHANX_POINTER(0x400)
#define ST40_DMAC_CHAN3_REQUEST ST40_DMAC_CHANX_REQUEST(0x400)
#define ST40_DMAC_CHAN3_CONTROL ST40_DMAC_CHANX_CONTROL(0x400)
#define ST40_DMAC_CHAN3_COUNT ST40_DMAC_CHANX_COUNT(0x400)
#define ST40_DMAC_CHAN3_SAR ST40_DMAC_CHANX_SAR(0x400)
#define ST40_DMAC_CHAN3_DAR ST40_DMAC_CHANX_DAR(0x400)
#define ST40_DMAC_CHAN3_NEXT_PTR ST40_DMAC_CHANX_NEXT_PTR(0x400)
#define ST40_DMAC_CHAN3_SRC_LENGTH ST40_DMAC_CHANX_SRC_LENGTH(0x400)
#define ST40_DMAC_CHAN3_SRC_STRIDE ST40_DMAC_CHANX_SRC_STRIDE(0x400)
#define ST40_DMAC_CHAN3_DST_LENGTH ST40_DMAC_CHANX_DST_LENGTH(0x400)
#define ST40_DMAC_CHAN3_DST_STRIDE ST40_DMAC_CHANX_DST_STRIDE(0x400)

#define ST40_DMAC_CHAN4_IDENTITY ST40_DMAC_CHANX_IDENTITY(0x500)
#define ST40_DMAC_CHAN4_ENABLE ST40_DMAC_CHANX_ENABLE(0x500)
#define ST40_DMAC_CHAN4_DISABLE ST40_DMAC_CHANX_DISABLE(0x500)
#define ST40_DMAC_CHAN4_STATUS ST40_DMAC_CHANX_STATUS(0x500)
#define ST40_DMAC_CHAN4_ACTION ST40_DMAC_CHANX_ACTION(0x500)
#define ST40_DMAC_CHAN4_POINTER ST40_DMAC_CHANX_POINTER(0x500)
#define ST40_DMAC_CHAN4_REQUEST ST40_DMAC_CHANX_REQUEST(0x500)
#define ST40_DMAC_CHAN4_CONTROL ST40_DMAC_CHANX_CONTROL(0x500)
#define ST40_DMAC_CHAN4_COUNT ST40_DMAC_CHANX_COUNT(0x500)
#define ST40_DMAC_CHAN4_SAR ST40_DMAC_CHANX_SAR(0x500)
#define ST40_DMAC_CHAN4_DAR ST40_DMAC_CHANX_DAR(0x500)
#define ST40_DMAC_CHAN4_NEXT_PTR ST40_DMAC_CHANX_NEXT_PTR(0x500)
#define ST40_DMAC_CHAN4_SRC_LENGTH ST40_DMAC_CHANX_SRC_LENGTH(0x500)
#define ST40_DMAC_CHAN4_SRC_STRIDE ST40_DMAC_CHANX_SRC_STRIDE(0x500)
#define ST40_DMAC_CHAN4_DST_LENGTH ST40_DMAC_CHANX_DST_LENGTH(0x500)
#define ST40_DMAC_CHAN4_DST_STRIDE ST40_DMAC_CHANX_DST_STRIDE(0x500)

#define ST40_DMAC_VCR_STATUS SH4_DWORD_REG(ST40_DMAC_REGS_BASE + 0x00)
#define ST40_DMAC_VCR_VERSION SH4_DWORD_REG(ST40_DMAC_REGS_BASE + 0x08)
#define ST40_DMAC_ENABLE SH4_DWORD_REG(ST40_DMAC_REGS_BASE + 0x10)
#define ST40_DMAC_DISABLE SH4_DWORD_REG(ST40_DMAC_REGS_BASE + 0x18)
#define ST40_DMAC_STATUS SH4_DWORD_REG(ST40_DMAC_REGS_BASE + 0x20)
#define ST40_DMAC_INTERRUPT SH4_DWORD_REG(ST40_DMAC_REGS_BASE + 0x28)
#define ST40_DMAC_ERROR SH4_DWORD_REG(ST40_DMAC_REGS_BASE + 0x30)