st40reg.h

来自「采用ST20 CPU的机顶盒的烧写程序」· C头文件 代码 · 共 615 行 · 第 1/3 页

#define ST40_PCI_CLS SH4_BYTE_REG(ST40_PCI_REGS_BASE + 0x01000c)
#define ST40_PCI_MLT SH4_BYTE_REG(ST40_PCI_REGS_BASE + 0x01000d)
#define ST40_PCI_HDR SH4_BYTE_REG(ST40_PCI_REGS_BASE + 0x01000e)
#define ST40_PCI_BIST SH4_BYTE_REG(ST40_PCI_REGS_BASE + 0x01000f)
#define ST40_PCI_MBAR0 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x010010)
#define ST40_PCI_IBAR SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x010018)
#define ST40_PCI_SVID SH4_WORD_REG(ST40_PCI_REGS_BASE + 0x01002c)
#define ST40_PCI_SID SH4_WORD_REG(ST40_PCI_REGS_BASE + 0x01002e)
#define ST40_PCI_CP SH4_BYTE_REG(ST40_PCI_REGS_BASE + 0x010034)
#define ST40_PCI_INTLINE SH4_BYTE_REG(ST40_PCI_REGS_BASE + 0x01003c)
#define ST40_PCI_INTPIN SH4_BYTE_REG(ST40_PCI_REGS_BASE + 0x01003d)
#define ST40_PCI_MINGNT SH4_BYTE_REG(ST40_PCI_REGS_BASE + 0x01003e)
#define ST40_PCI_MAXLAT SH4_BYTE_REG(ST40_PCI_REGS_BASE + 0x01003f)
#define ST40_PCI_TRDYTIME SH4_BYTE_REG(ST40_PCI_REGS_BASE + 0x010040)
#define ST40_PCI_RETRYTIME SH4_BYTE_REG(ST40_PCI_REGS_BASE + 0x010041)
#define ST40_PCI_CID SH4_BYTE_REG(ST40_PCI_REGS_BASE + 0x0100dc)
#define ST40_PCI_NIP SH4_BYTE_REG(ST40_PCI_REGS_BASE + 0x0100dd)
#define ST40_PCI_PMC SH4_WORD_REG(ST40_PCI_REGS_BASE + 0x0100de)
#define ST40_PCI_PMCSR SH4_WORD_REG(ST40_PCI_REGS_BASE + 0x0100e0)
#define ST40_PCI_PMCSR_BSE SH4_BYTE_REG(ST40_PCI_REGS_BASE + 0x0100e2)
#define ST40_PCI_PCDD SH4_BYTE_REG(ST40_PCI_REGS_BASE + 0x0100e3)

/* External MicroProcessor Interface control registers (all ST40 variants) */
#define ST40_EMPI_VCR_STATUS SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0000)
#define ST40_EMPI_VCR_VERSION SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0008)
#define ST40_EMPI_SYSTEM SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0010)
#define ST40_EMPI_ISTATUS SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0018)
#define ST40_EMPI_IMASK SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0020)
#define ST40_EMPI_MPXCFG SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0028)
#define ST40_EMPI_DMAINV SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0030)
#define ST40_EMPI_DMACFG0 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0080)
#define ST40_EMPI_DMACFG1 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0088)
#define ST40_EMPI_DMACFG2 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0090)
#define ST40_EMPI_DMACFG3 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0098)
#define ST40_EMPI_DSTATUS0 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0100)
#define ST40_EMPI_DSTATUS1 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0108)
#define ST40_EMPI_DSTATUS2 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0110)
#define ST40_EMPI_DSTATUS3 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0118)
#define ST40_EMPI_RBAR0 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0200)
#define ST40_EMPI_RSR0 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0208)
#define ST40_EMPI_RLAR0 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0210)
#define ST40_EMPI_RBAR1 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0220)
#define ST40_EMPI_RSR1 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0228)
#define ST40_EMPI_RLAR1 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0230)
#define ST40_EMPI_RBAR2 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0240)
#define ST40_EMPI_RSR2 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0248)
#define ST40_EMPI_RLAR2 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0250)
#define ST40_EMPI_RBAR3 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0260)
#define ST40_EMPI_RSR3 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0268)
#define ST40_EMPI_RLAR3 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0270)
#define ST40_EMPI_RBAR4 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0280)
#define ST40_EMPI_RSR4 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0288)
#define ST40_EMPI_RLAR4 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x0290)
#define ST40_EMPI_RBAR5 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x02a0)
#define ST40_EMPI_RSR5 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x02a8)
#define ST40_EMPI_RLAR5 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x02b0)
#define ST40_EMPI_RBAR6 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x02c0)
#define ST40_EMPI_RSR6 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x02c8)
#define ST40_EMPI_RLAR6 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x02d0)
#define ST40_EMPI_RBAR7 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x02e0)
#define ST40_EMPI_RSR7 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x02e8)
#define ST40_EMPI_RLAR7 SH4_DWORD_REG(ST40_EMPI_REGS_BASE + 0x02f0)

/* MPX Arbiter control registers (all ST40 variants) */
#define ST40_MPXARB_VCR SH4_DWORD_REG(ST40_MPXARB_REGS_BASE + 0x0000)
#define ST40_MPXARB_CONTROL SH4_DWORD_REG(ST40_MPXARB_REGS_BASE + 0x0010)
#define ST40_MPXARB_DLLCONTROL SH4_DWORD_REG(ST40_MPXARB_REGS_BASE + 0x4000)
#define ST40_MPXARB_DLLSTATUS SH4_DWORD_REG(ST40_MPXARB_REGS_BASE + 0x4010)

/* Mailbox control registers (all ST40 variants) */
#define ST40_MAILBOX_ID_VER(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0000)
#define ST40_MAILBOX_GROUP1_INTERRUPT_STATUS_REG1(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0004)
#define ST40_MAILBOX_GROUP1_INTERRUPT_STATUS_REG2(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0008)
#define ST40_MAILBOX_GROUP1_INTERRUPT_STATUS_REG3(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x000c)
#define ST40_MAILBOX_GROUP1_INTERRUPT_STATUS_REG4(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0010)
#define ST40_MAILBOX_GROUP1_INTERRUPT_STATUS_REG1_SET(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0024)
#define ST40_MAILBOX_GROUP1_INTERRUPT_STATUS_REG2_SET(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0028)
#define ST40_MAILBOX_GROUP1_INTERRUPT_STATUS_REG3_SET(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x002c)
#define ST40_MAILBOX_GROUP1_INTERRUPT_STATUS_REG4_SET(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0030)
#define ST40_MAILBOX_GROUP1_INTERRUPT_STATUS_REG1_CLR(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0044)
#define ST40_MAILBOX_GROUP1_INTERRUPT_STATUS_REG2_CLR(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0048)
#define ST40_MAILBOX_GROUP1_INTERRUPT_STATUS_REG3_CLR(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x004c)
#define ST40_MAILBOX_GROUP1_INTERRUPT_STATUS_REG4_CLR(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0050)
#define ST40_MAILBOX_GROUP1_INTERRUPT_ENABLE_REG1(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0064)
#define ST40_MAILBOX_GROUP1_INTERRUPT_ENABLE_REG2(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0068)
#define ST40_MAILBOX_GROUP1_INTERRUPT_ENABLE_REG3(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x006c)
#define ST40_MAILBOX_GROUP1_INTERRUPT_ENABLE_REG4(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0070)
#define ST40_MAILBOX_GROUP1_INTERRUPT_ENABLE_REG1_SET(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0084)
#define ST40_MAILBOX_GROUP1_INTERRUPT_ENABLE_REG2_SET(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0088)
#define ST40_MAILBOX_GROUP1_INTERRUPT_ENABLE_REG3_SET(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x008c)
#define ST40_MAILBOX_GROUP1_INTERRUPT_ENABLE_REG4_SET(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0090)
#define ST40_MAILBOX_GROUP1_INTERRUPT_ENABLE_REG1_CLR(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x00a4)
#define ST40_MAILBOX_GROUP1_INTERRUPT_ENABLE_REG2_CLR(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x00a8)
#define ST40_MAILBOX_GROUP1_INTERRUPT_ENABLE_REG3_CLR(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x00ac)
#define ST40_MAILBOX_GROUP1_INTERRUPT_ENABLE_REG4_CLR(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x00b0)
#define ST40_MAILBOX_GROUP2_INTERRUPT_STATUS_REG1(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0104)
#define ST40_MAILBOX_GROUP2_INTERRUPT_STATUS_REG2(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0108)
#define ST40_MAILBOX_GROUP2_INTERRUPT_STATUS_REG3(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x010c)
#define ST40_MAILBOX_GROUP2_INTERRUPT_STATUS_REG4(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0110)
#define ST40_MAILBOX_GROUP2_INTERRUPT_STATUS_REG1_SET(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0124)
#define ST40_MAILBOX_GROUP2_INTERRUPT_STATUS_REG2_SET(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0128)
#define ST40_MAILBOX_GROUP2_INTERRUPT_STATUS_REG3_SET(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x012c)
#define ST40_MAILBOX_GROUP2_INTERRUPT_STATUS_REG4_SET(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0130)
#define ST40_MAILBOX_GROUP2_INTERRUPT_STATUS_REG1_CLR(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0144)
#define ST40_MAILBOX_GROUP2_INTERRUPT_STATUS_REG2_CLR(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0148)
#define ST40_MAILBOX_GROUP2_INTERRUPT_STATUS_REG3_CLR(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x014c)
#define ST40_MAILBOX_GROUP2_INTERRUPT_STATUS_REG4_CLR(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0150)
#define ST40_MAILBOX_GROUP2_INTERRUPT_ENABLE_REG1(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0164)
#define ST40_MAILBOX_GROUP2_INTERRUPT_ENABLE_REG2(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0168)
#define ST40_MAILBOX_GROUP2_INTERRUPT_ENABLE_REG3(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x016c)
#define ST40_MAILBOX_GROUP2_INTERRUPT_ENABLE_REG4(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0170)
#define ST40_MAILBOX_GROUP2_INTERRUPT_ENABLE_REG1_SET(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0184)
#define ST40_MAILBOX_GROUP2_INTERRUPT_ENABLE_REG2_SET(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0188)
#define ST40_MAILBOX_GROUP2_INTERRUPT_ENABLE_REG3_SET(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x018c)
#define ST40_MAILBOX_GROUP2_INTERRUPT_ENABLE_REG4_SET(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0190)
#define ST40_MAILBOX_GROUP2_INTERRUPT_ENABLE_REG1_CLR(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x01a4)
#define ST40_MAILBOX_GROUP2_INTERRUPT_ENABLE_REG2_CLR(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x01a8)
#define ST40_MAILBOX_GROUP2_INTERRUPT_ENABLE_REG3_CLR(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x01ac)
#define ST40_MAILBOX_GROUP2_INTERRUPT_ENABLE_REG4_CLR(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x01b0)
#define ST40_MAILBOX_LOCK0(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0200)
#define ST40_MAILBOX_LOCK1(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0204)
#define ST40_MAILBOX_LOCK2(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0208)
#define ST40_MAILBOX_LOCK3(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x020c)
#define ST40_MAILBOX_LOCK4(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0210)
#define ST40_MAILBOX_LOCK5(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0214)
#define ST40_MAILBOX_LOCK6(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0218)
#define ST40_MAILBOX_LOCK7(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x021c)
#define ST40_MAILBOX_LOCK8(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0220)
#define ST40_MAILBOX_LOCK9(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0224)
#define ST40_MAILBOX_LOCK10(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0228)
#define ST40_MAILBOX_LOCK11(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x022c)
#define ST40_MAILBOX_LOCK12(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0230)
#define ST40_MAILBOX_LOCK13(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0234)
#define ST40_MAILBOX_LOCK14(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0238)
#define ST40_MAILBOX_LOCK15(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x023c)
#define ST40_MAILBOX_LOCK16(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0240)
#define ST40_MAILBOX_LOCK17(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0244)
#define ST40_MAILBOX_LOCK18(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0248)
#define ST40_MAILBOX_LOCK19(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x024c)
#define ST40_MAILBOX_LOCK20(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0250)
#define ST40_MAILBOX_LOCK21(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0254)
#define ST40_MAILBOX_LOCK22(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0258)
#define ST40_MAILBOX_LOCK23(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x025c)
#define ST40_MAILBOX_LOCK24(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0260)
#define ST40_MAILBOX_LOCK25(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0264)
#define ST40_MAILBOX_LOCK26(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0268)
#define ST40_MAILBOX_LOCK27(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x026c)
#define ST40_MAILBOX_LOCK28(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0270)
#define ST40_MAILBOX_LOCK29(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0274)
#define ST40_MAILBOX_LOCK30(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x0278)
#define ST40_MAILBOX_LOCK31(n) SH4_DWORD_REG(ST40_MAILBOX##n##_REGS_BASE + 0x027c)

/* System configuration registers (all ST40 variants) */
#define ST40_SYSCONF_VCR SH4_DWORD_REG(ST40_SYSCONF_REGS_BASE + 0x00)
#define ST40_SYSCONF_SYS_CON1_0 SH4_DWORD_REG(ST40_SYSCONF_REGS_BASE + 0x10)
#define ST40_SYSCONF_SYS_CON1_1 SH4_DWORD_REG(ST40_SYSCONF_REGS_BASE + 0x14)
#define ST40_SYSCONF_SYS_CON1 SH4_GWORD_REG(ST40_SYSCONF_REGS_BASE + 0x10)
#define ST40_SYSCONF_SYS_CON2_0 SH4_DWORD_REG(ST40_SYSCONF_REGS_BASE + 0x18)
#define ST40_SYSCONF_SYS_CON2_1 SH4_DWORD_REG(ST40_SYSCONF_REGS_BASE + 0x1c)
#define ST40_SYSCONF_SYS_CON2 SH4_GWORD_REG(ST40_SYSCONF_REGS_BASE + 0x18)
#define ST40_SYSCONF_CNV_STATUS SH4_BYTE_REG(ST40_SYSCONF_REGS_BASE + 0x20)
#define ST40_SYSCONF_CNV_SET SH4_BYTE_REG(ST40_SYSCONF_REGS_BASE + 0x28)
#define ST40_SYSCONF_CNV_CLEAR SH4_BYTE_REG(ST40_SYSCONF_REGS_BASE + 0x30)
#define ST40_SYSCONF_CNV_CONTROL SH4_DWORD_REG(ST40_SYSCONF_REGS_BASE + 0x38)
#define ST40_SYSCONF_SYS_STAT1_0 SH4_DWORD_REG(ST40_SYSCONF_REGS_BASE + 0x40)
#define ST40_SYSCONF_SYS_STAT1_1 SH4_DWORD_REG(ST40_SYSCONF_REGS_BASE + 0x44)
#define ST40_SYSCONF_SYS_STAT1 SH4_GWORD_REG(ST40_SYSCONF_REGS_BASE + 0x40)
#define ST40_SYSCONF_SYS_STAT2_0 SH4_DWORD_REG(ST40_SYSCONF_REGS_BASE + 0x48)
#define ST40_SYSCONF_SYS_STAT2_1 SH4_DWORD_REG(ST40_SYSCONF_REGS_BASE + 0x4c)
#define ST40_SYSCONF_SYS_STAT2 SH4_GWORD_REG(ST40_SYSCONF_REGS_BASE + 0x48)

/* Synchronous Serial Controller control registers (all ST40 variants) */
#define ST40_SSC_BRG(n) SH4_WORD_REG(ST40_SSC##n##_REGS_BASE + 0x0000)
#define ST40_SSC_TBUF(n) SH4_WORD_REG(ST40_SSC##n##_REGS_BASE + 0x0004)
#define ST40_SSC_RBUF(n) SH4_WORD_REG(ST40_SSC##n##_REGS_BASE + 0x0008)
#define ST40_SSC_CTL(n) SH4_WORD_REG(ST40_SSC##n##_REGS_BASE + 0x000c)
#define ST40_SSC_IEN(n) SH4_WORD_REG(ST40_SSC##n##_REGS_BASE + 0x0010)
#define ST40_SSC_STA(n) SH4_WORD_REG(ST40_SSC##n##_REGS_BASE + 0x0014)
#define ST40_SSC_I2C(n) SH4_WORD_REG(ST40_SSC##n##_REGS_BASE + 0x0018)
#define ST40_SSC_SLAD(n) SH4_WORD_REG(ST40_SSC##n##_REGS_BASE + 0x001c)
#define ST40_SSC_REP_START_HOLD(n) SH4_WORD_REG(ST40_SSC##n##_REGS_BASE + 0x0020)
#define ST40_SSC_START_HOLD(n) SH4_WORD_REG(ST40_SSC##n##_REGS_BASE + 0x0024)
#define ST40_SSC_REP_START_SETUP(n) SH4_WORD_REG(ST40_SSC##n##_REGS_BASE + 0x0028)
#define ST40_SSC_DATA_SETUP(n) SH4_WORD_REG(ST40_SSC##n##_REGS_BASE + 0x002c)
#define ST40_SSC_STOP_SETUP(n) SH4_WORD_REG(ST40_SSC##n##_REGS_BASE + 0x0030)
#define ST40_SSC_BUS_FREE(n) SH4_WORD_REG(ST40_SSC##n##_REGS_BASE + 0x0034)
#define ST40_SSC_CLR_STA(n) SH4_DWORD_REG(ST40_SSC##n##_REGS_BASE + 0x0080)
#define ST40_SSC_AGFR(n) SH4_DWORD_REG(ST40_SSC##n##_REGS_BASE + 0x0100)
#define ST40_SSC_PRSC(n) SH4_DWORD_REG(ST40_SSC##n##_REGS_BASE + 0x0104)

/* Asynchronous Serial Controller control registers (all ST40 variants) */
#define ST40_ASC_BAUDRATE(n) SH4_DWORD_REG(ST40_ASC##n##_REGS_BASE + 0x00)
#define ST40_ASC_TXBUFFER(n) SH4_DWORD_REG(ST40_ASC##n##_REGS_BASE + 0x04)
#define ST40_ASC_RXBUFFER(n) SH4_DWORD_REG(ST40_ASC##n##_REGS_BASE + 0x08)
#define ST40_ASC_CONTROL(n) SH4_DWORD_REG(ST40_ASC##n##_REGS_BASE + 0x0c)
#define ST40_ASC_INTENABLE(n) SH4_DWORD_REG(ST40_ASC##n##_REGS_BASE + 0x10)
#define ST40_ASC_STATUS(n) SH4_DWORD_REG(ST40_ASC##n##_REGS_BASE + 0x14)
#define ST40_ASC_GUARDTIME(n) SH4_DWORD_REG(ST40_ASC##n##_REGS_BASE + 0x18)
#define ST40_ASC_TIMEOUT(n) SH4_DWORD_REG(ST40_ASC##n##_REGS_BASE + 0x1c)
#define ST40_ASC_TXRESET(n) SH4_DWORD_REG(ST40_ASC##n##_REGS_BASE + 0x20)
#define ST40_ASC_RXRESET(n) SH4_DWORD_REG(ST40_ASC##n##_REGS_BASE + 0x24)
#define ST40_ASC_RETRIES(n) SH4_DWORD_REG(ST40_ASC##n##_REGS_BASE + 0x28)

#endif /* __ST40REG_H */