st40reg.h

来自「采用ST20 CPU的机顶盒的烧写程序」· C头文件 代码 · 共 615 行 · 第 1/3 页

#define ST40_DMAC_DEFINED SH4_DWORD_REG(ST40_DMAC_REGS_BASE + 0x38)
#define ST40_DMAC_HANDSHAKE SH4_DWORD_REG(ST40_DMAC_REGS_BASE + 0x40)

/* Parallel I/O control registers (all ST40 variants) */
#define ST40_PIO_POUT(n) SH4_DWORD_REG(ST40_PIO##n##_REGS_BASE + 0x00)
#define ST40_PIO_PIN(n) SH4_DWORD_REG(ST40_PIO##n##_REGS_BASE + 0x10)
#define ST40_PIO_PC0(n) SH4_DWORD_REG(ST40_PIO##n##_REGS_BASE + 0x20)
#define ST40_PIO_PC1(n) SH4_DWORD_REG(ST40_PIO##n##_REGS_BASE + 0x30)
#define ST40_PIO_PC2(n) SH4_DWORD_REG(ST40_PIO##n##_REGS_BASE + 0x40)
#define ST40_PIO_PCOMP(n) SH4_DWORD_REG(ST40_PIO##n##_REGS_BASE + 0x50)
#define ST40_PIO_PMASK(n) SH4_DWORD_REG(ST40_PIO##n##_REGS_BASE + 0x60)

/* PIO pseudo registers */
#define ST40_PIO_SET_POUT(n) SH4_DWORD_REG(ST40_PIO##n##_REGS_BASE + 0x04)
#define ST40_PIO_CLEAR_POUT(n) SH4_DWORD_REG(ST40_PIO##n##_REGS_BASE + 0x08)
#define ST40_PIO_SET_PC0(n) SH4_DWORD_REG(ST40_PIO##n##_REGS_BASE + 0x24)
#define ST40_PIO_CLEAR_PC0(n) SH4_DWORD_REG(ST40_PIO##n##_REGS_BASE + 0x28)
#define ST40_PIO_SET_PC1(n) SH4_DWORD_REG(ST40_PIO##n##_REGS_BASE + 0x34)
#define ST40_PIO_CLEAR_PC1(n) SH4_DWORD_REG(ST40_PIO##n##_REGS_BASE + 0x38)
#define ST40_PIO_SET_PC2(n) SH4_DWORD_REG(ST40_PIO##n##_REGS_BASE + 0x44)
#define ST40_PIO_CLEAR_PC2(n) SH4_DWORD_REG(ST40_PIO##n##_REGS_BASE + 0x48)
#define ST40_PIO_SET_PCOMP(n) SH4_DWORD_REG(ST40_PIO##n##_REGS_BASE + 0x54)
#define ST40_PIO_CLEAR_PCOMP(n) SH4_DWORD_REG(ST40_PIO##n##_REGS_BASE + 0x58)
#define ST40_PIO_SET_PMASK(n) SH4_DWORD_REG(ST40_PIO##n##_REGS_BASE + 0x64)
#define ST40_PIO_CLEAR_PMASK(n) SH4_DWORD_REG(ST40_PIO##n##_REGS_BASE + 0x68)

/* Local Memory Interface control registers (all ST40 variants).
   Define ST40_LMI_VERSION for standard LMIs and ST40_LMIGP_VERSION for GP LMIs.
 */
#if !(defined(ST40_LMI_VERSION) || defined(ST40_LMIGP_VERSION))
/* For variants which do not define which LMI they have we define
   ST40_LMI_VERSION 2 as the default.
 */
#define ST40_LMI_VERSION 2
#endif
#if defined(ST40_LMI_VERSION)
#define ST40_LMI_VCR_0(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000000)
#define ST40_LMI_VCR_1(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000004)
#define ST40_LMI_VCR(n) SH4_GWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000000)
#define ST40_LMI_MIM_0(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000008)
#define ST40_LMI_MIM_1(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x00000c)
#define ST40_LMI_MIM(n) SH4_GWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000008)
#define ST40_LMI_SCR_0(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000010)
#define ST40_LMI_SCR_1(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000014)
#define ST40_LMI_SCR(n) SH4_GWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000010)
#define ST40_LMI_STR_0(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000018)
#define ST40_LMI_STR_1(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x00001c)
#define ST40_LMI_STR(n) SH4_GWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000018)
#define ST40_LMI_PBS_0(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000020)
#define ST40_LMI_PBS_1(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000024)
#define ST40_LMI_PBS(n) SH4_GWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000020)
#define ST40_LMI_COC_0(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000028)
#define ST40_LMI_COC_1(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x00002c)
#define ST40_LMI_COC(n) SH4_GWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000028)
#define ST40_LMI_SDRA0_0(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000030)
#define ST40_LMI_SDRA0_1(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000034)
#define ST40_LMI_SDRA0(n) SH4_GWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000030)
#define ST40_LMI_SDRA1_0(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000038)
#define ST40_LMI_SDRA1_1(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x00003c)
#define ST40_LMI_SDRA1(n) SH4_GWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000038)
#define ST40_LMI_CIC_0(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000040)
#define ST40_LMI_CIC_1(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000044)
#define ST40_LMI_CIC(n) SH4_GWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000040)
#if (ST40_LMI_VERSION > 2)
#define ST40_LMI_SDMR0(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000048)
#define ST40_LMI_SDMR1(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000050)
#else
#define ST40_LMI_SDMR0(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x800000)
#define ST40_LMI_SDMR1(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x900000)
#endif
#elif defined(ST40_LMIGP_VERSION)
#define ST40_LMI_VCR_0(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000000)
#define ST40_LMI_VCR_1(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000004)
#define ST40_LMI_VCR(n) SH4_GWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000000)
#define ST40_LMI_MIM_0(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000008)
#define ST40_LMI_MIM_1(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x00000c)
#define ST40_LMI_MIM(n) SH4_GWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000008)
#define ST40_LMI_SCR_0(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000010)
#define ST40_LMI_SCR_1(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000014)
#define ST40_LMI_SCR(n) SH4_GWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000010)
#define ST40_LMI_STR_0(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000018)
#define ST40_LMI_STR_1(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x00001c)
#define ST40_LMI_STR(n) SH4_GWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000018)
#define ST40_LMI_GCC_0(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000028)
#define ST40_LMI_GCC_1(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x00002c)
#define ST40_LMI_GCC(n) SH4_GWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000028)
#define ST40_LMI_SDRA0_0(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000030)
#define ST40_LMI_SDRA0_1(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000034)
#define ST40_LMI_SDRA0(n) SH4_GWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000030)
#define ST40_LMI_SDRA1_0(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000038)
#define ST40_LMI_SDRA1_1(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x00003c)
#define ST40_LMI_SDRA1(n) SH4_GWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000038)
#define ST40_LMI_CCO_0(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000040)
#define ST40_LMI_CCO_1(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000044)
#define ST40_LMI_CCO(n) SH4_GWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000040)
#define ST40_LMI_SDMR0(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000048)
#define ST40_LMI_SDMR1(n) SH4_DWORD_REG(ST40_LMI##n##_REGS_BASE + 0x000050)
#endif

/* Enhanced Flash Memory Interface control registers (all ST40 variants) */
#define ST40_EMI_VCR_0 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0000)
#define ST40_EMI_VCR_1 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0004)
#define ST40_EMI_VCR SH4_GWORD_REG(ST40_EMI_REGS_BASE + 0x0000)
#define ST40_EMI_STATUSCFG SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0010)
#define ST40_EMI_STATUSLOCK SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0018)
#define ST40_EMI_LOCK SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0020)
#define ST40_EMI_GENCFG SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0028)
#define ST40_EMI_SDRAMNOPGEN SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0030)
#define ST40_EMI_SDRAMMODEREG SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0038)
#define ST40_EMI_SDRAMINIT SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0040)
#define ST40_EMI_REFRESHINIT SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0048)
#define ST40_EMI_FLASHCLKSEL SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0050)
#define ST40_EMI_SDRAMCLKSEL SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0058)
#define ST40_EMI_MPXCLKSEL SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0060)
#define ST40_EMI_CLKENABLE SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0068)
#define ST40_EMI_BANK0_EMICONFIGDATA0 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0100)
#define ST40_EMI_BANK0_EMICONFIGDATA1 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0108)
#define ST40_EMI_BANK0_EMICONFIGDATA2 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0110)
#define ST40_EMI_BANK0_EMICONFIGDATA3 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0118)
#define ST40_EMI_BANK1_EMICONFIGDATA0 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0140)
#define ST40_EMI_BANK1_EMICONFIGDATA1 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0148)
#define ST40_EMI_BANK1_EMICONFIGDATA2 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0150)
#define ST40_EMI_BANK1_EMICONFIGDATA3 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0158)
#define ST40_EMI_BANK2_EMICONFIGDATA0 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0180)
#define ST40_EMI_BANK2_EMICONFIGDATA1 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0188)
#define ST40_EMI_BANK2_EMICONFIGDATA2 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0190)
#define ST40_EMI_BANK2_EMICONFIGDATA3 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0198)
#define ST40_EMI_BANK3_EMICONFIGDATA0 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x01c0)
#define ST40_EMI_BANK3_EMICONFIGDATA1 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x01c8)
#define ST40_EMI_BANK3_EMICONFIGDATA2 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x01d0)
#define ST40_EMI_BANK3_EMICONFIGDATA3 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x01d8)
#define ST40_EMI_BANK4_EMICONFIGDATA0 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0200)
#define ST40_EMI_BANK4_EMICONFIGDATA1 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0208)
#define ST40_EMI_BANK4_EMICONFIGDATA2 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0210)
#define ST40_EMI_BANK4_EMICONFIGDATA3 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0218)
#define ST40_EMI_BANK5_EMICONFIGDATA0 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0240)
#define ST40_EMI_BANK5_EMICONFIGDATA1 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0248)
#define ST40_EMI_BANK5_EMICONFIGDATA2 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0250)
#define ST40_EMI_BANK5_EMICONFIGDATA3 SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0258)
#define ST40_EMI_BANK_ENABLE SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0280)

#define ST40_EMI_BANK0_BASEADDRESS SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0800)
#define ST40_EMI_BANK1_BASEADDRESS SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0810)
#define ST40_EMI_BANK2_BASEADDRESS SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0820)
#define ST40_EMI_BANK3_BASEADDRESS SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0830)
#define ST40_EMI_BANK4_BASEADDRESS SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0840)
#define ST40_EMI_BANK5_BASEADDRESS SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0850)
#define ST40_EMI_BANKNUMBER SH4_DWORD_REG(ST40_EMI_REGS_BASE + 0x0860)

/* Peripheral Component Interconnect control registers (all ST40 variants) */
/* PCI Local Registers */
#define ST40_PCI_VCR_STATUS SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000000)
#define ST40_PCI_VCR_VERSION SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000008)
#define ST40_PCI_CR SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000010)
#define ST40_PCI_LSR0 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000014)
#define ST40_PCI_LAR0 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x00001c)
#define ST40_PCI_INT SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000024)
#define ST40_PCI_INTM SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000028)
#define ST40_PCI_AIR SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x00002c)
#define ST40_PCI_CIR SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000030)
#define ST40_PCI_AINT SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000040)
#define ST40_PCI_AINTM SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000044)
#define ST40_PCI_BMIR SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000048)
#define ST40_PCI_PAR SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x00004c)
#define ST40_PCI_MBR SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000050)
#define ST40_PCI_IOBR SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000054)
#define ST40_PCI_PINT SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000058)
#define ST40_PCI_PINTM SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x00005c)
#define ST40_PCI_MBMR SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000070)
#define ST40_PCI_IOBMR SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000074)

/* PCI Local Configuration Registers */
#define ST40_PCI_WCBAR SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x00007c)
#define ST40_PCI_LOCCFG_UNLOCK SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000034)
#define ST40_PCI_RBARR0 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000100)
#define ST40_PCI_RSR0 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000104)
#define ST40_PCI_RLAR0 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000108)
#define ST40_PCI_RBARR1 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000110)
#define ST40_PCI_RSR1 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000114)
#define ST40_PCI_RLAR1 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000118)
#define ST40_PCI_RBARR2 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000120)
#define ST40_PCI_RSR2 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000124)
#define ST40_PCI_RLAR2 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000128)
#define ST40_PCI_RBARR3 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000130)
#define ST40_PCI_RSR3 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000134)
#define ST40_PCI_RLAR3 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000138)
#define ST40_PCI_RBARR4 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000140)
#define ST40_PCI_RSR4 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000144)
#define ST40_PCI_RLAR4 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000148)
#define ST40_PCI_RBARR5 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000150)
#define ST40_PCI_RSR5 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000154)
#define ST40_PCI_RLAR5 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000158)
#define ST40_PCI_RBARR6 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000160)
#define ST40_PCI_RSR6 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000164)
#define ST40_PCI_RLAR6 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000168)
#define ST40_PCI_RBARR7 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000170)
#define ST40_PCI_RSR7 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000174)
#define ST40_PCI_RLAR7 SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x000178)

/* PCI Configuration Space Registers (CSR) */
#define ST40_PCI_VID SH4_WORD_REG(ST40_PCI_REGS_BASE + 0x010000)
#define ST40_PCI_DID SH4_WORD_REG(ST40_PCI_REGS_BASE + 0x010002)
#define ST40_PCI_CMD SH4_WORD_REG(ST40_PCI_REGS_BASE + 0x010004)
#define ST40_PCI_STATUS SH4_WORD_REG(ST40_PCI_REGS_BASE + 0x010006)
#define ST40_PCI_RID_CLASS SH4_DWORD_REG(ST40_PCI_REGS_BASE + 0x010008)