sine.tan.rpt

来自「原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm」· RPT 代码 · 共 207 行 · 第 1/5 页

; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[2]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg1 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[2]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg2 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[2]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg3 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[2]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg4 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[2]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg5 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[2]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[1]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg1 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[1]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg2 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[1]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg3 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[1]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg4 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[1]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg5 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[1]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg1 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg2 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg3 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg4 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg5 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; q1[3]                                                                                                                              ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg3 ; clk        ; clk      ; None                        ; None                      ; 2.255 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; q1[0]                                                                                                                              ; q1[5]                                                                                                                              ; clk        ; clk      ; None                        ; None                      ; 2.101 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; q1[1]                                                                                                                              ; q1[5]                                                                                                                              ; clk        ; clk      ; None                        ; None                      ; 2.065 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; q1[0]                                                                                                                              ; q1[4]                                                                                                                              ; clk        ; clk      ; None                        ; None                      ; 2.015 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; q1[2]                                                                                                                              ; q1[5]                                                                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.979 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; q1[1]                                                                                                                              ; q1[4]                                                                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.979 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; q1[2]                                                                                                                              ; q1[4]                                                                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.893 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; q1[3]                                                                                                                              ; q1[5]                                                                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.849 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; q1[0]                                                                                                                              ; q1[3]                                                                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.825 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; q1[1]                                                                                                                              ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg1 ; clk        ; clk      ; None                        ; None                      ; 1.822 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; q1[1]                                                                                                                              ; q1[3]                                                                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.789 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; q1[3]                                                                                                                              ; q1[4]                                                                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.763 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; q1[0]                                                                                                                              ; q1[2]                                                                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.739 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; q1[2]                                                                                                                              ; q1[3]                                                                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.703 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; q1[1]                                                                                                                              ; q1[2]                                                                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.703 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; q1[4]                                                                                                                              ; q1[5]                                                                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.694 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; q1[0]                                                                                                                              ; q1[1]                                                                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.653 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; q1[5]                                                                                                                              ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg5 ; clk        ; clk      ; None                        ; None                      ; 1.462 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; q1[2]                                                                                                                              ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg2 ; clk        ; clk      ; None                        ; None                      ; 1.460 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; q1[4]                                                                                                                              ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg4 ; clk        ; clk      ; None                        ; None                      ; 1.457 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; q1[2]                                                                                                                              ; q1[2]                                                                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.223 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; q1[1]                                                                                                                              ; q1[1]                                                                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.223 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; q1[4]                                                                                                                              ; q1[4]                                                                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.214 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; q1[0]                                                                                                                              ; q1[0]                                                                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.175 ns                ;