sine.tan.rpt

来自「原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm」· RPT 代码 · 共 207 行 · 第 1/5 页

; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk                          ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+-------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                                                                               ; To                                                                                                                                 ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg1 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg2 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg3 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg4 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg5 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg1 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg2 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg3 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg4 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg5 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg1 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg2 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg3 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg4 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg5 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[4]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg1 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[4]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg2 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[4]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg3 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[4]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg4 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[4]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg5 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[4]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[3]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg1 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[3]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg2 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[3]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg3 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[3]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg4 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[3]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg5 ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[3]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;