sine.tan.qmsg

原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成

{ "Info" "ITDB_TSU_RESULT" "sld_hub:sld_hub_inst\|jtag_debug_mode altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP 2.919 ns register " "Info: tsu for register \"sld_hub:sld_hub_inst\|jtag_debug_mode\" (data pin = \"altera_internal_jtag~TMSUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 2.919 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.587 ns + Longest pin register " "Info: + Longest pin to register delay is 6.587 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TMSUTAP 1 PIN JTAG_X1_Y19_N0 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 23; PIN Node = 'altera_internal_jtag~TMSUTAP'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { altera_internal_jtag~TMSUTAP } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.824 ns) + CELL(0.624 ns) 4.448 ns sld_hub:sld_hub_inst\|jtag_debug_mode~171 2 COMB LCCOMB_X46_Y20_N4 1 " "Info: 2: + IC(3.824 ns) + CELL(0.624 ns) = 4.448 ns; Loc. = LCCOMB_X46_Y20_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode~171'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "4.448 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|jtag_debug_mode~171 } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 382 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.407 ns) + CELL(0.624 ns) 6.479 ns sld_hub:sld_hub_inst\|jtag_debug_mode~172 3 COMB LCCOMB_X46_Y21_N30 1 " "Info: 3: + IC(1.407 ns) + CELL(0.624 ns) = 6.479 ns; Loc. = LCCOMB_X46_Y21_N30; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode~172'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "2.031 ns" { sld_hub:sld_hub_inst|jtag_debug_mode~171 sld_hub:sld_hub_inst|jtag_debug_mode~172 } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 382 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.587 ns sld_hub:sld_hub_inst\|jtag_debug_mode 4 REG LCFF_X46_Y21_N31 3 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 6.587 ns; Loc. = LCFF_X46_Y21_N31; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "0.108 ns" { sld_hub:sld_hub_inst|jtag_debug_mode~172 sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 382 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.356 ns ( 20.59 % ) " "Info: Total cell delay = 1.356 ns ( 20.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.231 ns ( 79.41 % ) " "Info: Total interconnect delay = 5.231 ns ( 79.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "6.587 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|jtag_debug_mode~171 sld_hub:sld_hub_inst|jtag_debug_mode~172 sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.587 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|jtag_debug_mode~171 sld_hub:sld_hub_inst|jtag_debug_mode~172 sld_hub:sld_hub_inst|jtag_debug_mode } { 0.000ns 3.824ns 1.407ns 0.000ns } { 0.000ns 0.624ns 0.624ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 382 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 3.628 ns - Shortest register " "Info: - Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 3.628 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.766 ns) + CELL(0.000 ns) 1.766 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 126 " "Info: 2: + IC(1.766 ns) + CELL(0.000 ns) = 1.766 ns; Loc. = CLKCTRL_G0; Fanout = 126; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "1.766 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.196 ns) + CELL(0.666 ns) 3.628 ns sld_hub:sld_hub_inst\|jtag_debug_mode 3 REG LCFF_X46_Y21_N31 3 " "Info: 3: + IC(1.196 ns) + CELL(0.666 ns) = 3.628 ns; Loc. = LCFF_X46_Y21_N31; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "1.862 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 382 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 18.36 % ) " "Info: Total cell delay = 0.666 ns ( 18.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.962 ns ( 81.64 % ) " "Info: Total interconnect delay = 2.962 ns ( 81.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "3.628 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.628 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode } { 0.000ns 1.766ns 1.196ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "6.587 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|jtag_debug_mode~171 sld_hub:sld_hub_inst|jtag_debug_mode~172 sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.587 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|jtag_debug_mode~171 sld_hub:sld_hub_inst|jtag_debug_mode~172 sld_hub:sld_hub_inst|jtag_debug_mode } { 0.000ns 3.824ns 1.407ns 0.000ns } { 0.000ns 0.624ns 0.624ns 0.108ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "3.628 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.628 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode } { 0.000ns 1.766ns 1.196ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout\[3\] rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|altsyncram_b192:altsyncram1\|q_a\[3\] 8.983 ns memory " "Info: tco from clock \"clk\" to destination pin \"dout\[3\]\" through memory \"rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|altsyncram_b192:altsyncram1\|q_a\[3\]\" is 8.983 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.159 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 3.159 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { clk } "NODE_NAME" } "" } } { "sine.vhd" "" { Text "D:/quartus/myproject/正弦信号发生器/sine.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G3 20 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G3; Fanout = 20; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "sine.vhd" "" { Text "D:/quartus/myproject/正弦信号发生器/sine.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.115 ns) + CELL(0.815 ns) 3.159 ns rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|altsyncram_b192:altsyncram1\|q_a\[3\] 3 MEM M4K_X52_Y21 1 " "Info: 3: + IC(1.115 ns) + CELL(0.815 ns) = 3.159 ns; Loc. = M4K_X52_Y21; Fanout = 1; MEM Node = 'rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|altsyncram_b192:altsyncram1\|q_a\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "1.930 ns" { clk~clkctrl rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[3] } "NODE_NAME" } "" } } { "db/altsyncram_b192.tdf" "" { Text "D:/quartus/myproject/正弦信号发生器/db/altsyncram_b192.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.905 ns ( 60.30 % ) " "Info: Total cell delay = 1.905 ns ( 60.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.254 ns ( 39.70 % ) " "Info: Total interconnect delay = 1.254 ns ( 39.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "3.159 ns" { clk clk~clkctrl rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.159 ns" { clk clk~combout clk~clkctrl rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[3] } { 0.000ns 0.000ns 0.139ns 1.115ns } { 0.000ns 1.090ns 0.000ns 0.815ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_b192.tdf" "" { Text "D:/quartus/myproject/正弦信号发生器/db/altsyncram_b192.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.564 ns + Longest memory pin " "Info: + Longest memory to pin delay is 5.564 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.109 ns) 0.109 ns rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|altsyncram_b192:altsyncram1\|q_a\[3\] 1 MEM M4K_X52_Y21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.109 ns) = 0.109 ns; Loc. = M4K_X52_Y21; Fanout = 1; MEM Node = 'rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|altsyncram_b192:altsyncram1\|q_a\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[3] } "NODE_NAME" } "" } } { "db/altsyncram_b192.tdf" "" { Text "D:/quartus/myproject/正弦信号发生器/db/altsyncram_b192.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.419 ns) + CELL(3.036 ns) 5.564 ns dout\[3\] 2 PIN PIN_H22 0 " "Info: 2: + IC(2.419 ns) + CELL(3.036 ns) = 5.564 ns; Loc. = PIN_H22; Fanout = 0; PIN Node = 'dout\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "5.455 ns" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[3] dout[3] } "NODE_NAME" } "" } } { "sine.vhd" "" { Text "D:/quartus/myproject/正弦信号发生器/sine.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.145 ns ( 56.52 % ) " "Info: Total cell delay = 3.145 ns ( 56.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.419 ns ( 43.48 % ) " "Info: Total interconnect delay = 2.419 ns ( 43.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "5.564 ns" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[3] dout[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.564 ns" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[3] dout[3] } { 0.000ns 2.419ns } { 0.109ns 3.036ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "3.159 ns" { clk clk~clkctrl rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.159 ns" { clk clk~combout clk~clkctrl rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[3] } { 0.000ns 0.000ns 0.139ns 1.115ns } { 0.000ns 1.090ns 0.000ns 0.815ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "5.564 ns" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[3] dout[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.564 ns" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[3] dout[3] } { 0.000ns 2.419ns } { 0.109ns 3.036ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}