sine.tan.qmsg

原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk memory memory rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|altsyncram_b192:altsyncram1\|ram_block3a0~porta_address_reg0 rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|altsyncram_b192:altsyncram1\|q_a\[7\] 163.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 163.03 MHz between source memory \"rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|altsyncram_b192:altsyncram1\|ram_block3a0~porta_address_reg0\" and destination memory \"rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|altsyncram_b192:altsyncram1\|q_a\[7\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "3.067 ns 3.067 ns 6.134 ns " "Info: fmax restricted to Clock High delay (3.067 ns) plus Clock Low delay (3.067 ns) : restricted to 6.134 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.641 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.641 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|altsyncram_b192:altsyncram1\|ram_block3a0~porta_address_reg0 1 MEM M4K_X52_Y21 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X52_Y21; Fanout = 8; MEM Node = 'rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|altsyncram_b192:altsyncram1\|ram_block3a0~porta_address_reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_b192.tdf" "" { Text "D:/quartus/myproject/正弦信号发生器/db/altsyncram_b192.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.641 ns) 3.641 ns rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|altsyncram_b192:altsyncram1\|q_a\[7\] 2 MEM M4K_X52_Y21 1 " "Info: 2: + IC(0.000 ns) + CELL(3.641 ns) = 3.641 ns; Loc. = M4K_X52_Y21; Fanout = 1; MEM Node = 'rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|altsyncram_b192:altsyncram1\|q_a\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "3.641 ns" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7] } "NODE_NAME" } "" } } { "db/altsyncram_b192.tdf" "" { Text "D:/quartus/myproject/正弦信号发生器/db/altsyncram_b192.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.641 ns ( 100.00 % ) " "Info: Total cell delay = 3.641 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "3.641 ns" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.641 ns" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7] } { 0.000ns 0.000ns } { 0.000ns 3.641ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.020 ns - Smallest " "Info: - Smallest clock skew is -0.020 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.159 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 3.159 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { clk } "NODE_NAME" } "" } } { "sine.vhd" "" { Text "D:/quartus/myproject/正弦信号发生器/sine.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G3 20 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G3; Fanout = 20; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "sine.vhd" "" { Text "D:/quartus/myproject/正弦信号发生器/sine.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.115 ns) + CELL(0.815 ns) 3.159 ns rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|altsyncram_b192:altsyncram1\|q_a\[7\] 3 MEM M4K_X52_Y21 1 " "Info: 3: + IC(1.115 ns) + CELL(0.815 ns) = 3.159 ns; Loc. = M4K_X52_Y21; Fanout = 1; MEM Node = 'rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|altsyncram_b192:altsyncram1\|q_a\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "1.930 ns" { clk~clkctrl rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7] } "NODE_NAME" } "" } } { "db/altsyncram_b192.tdf" "" { Text "D:/quartus/myproject/正弦信号发生器/db/altsyncram_b192.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.905 ns ( 60.30 % ) " "Info: Total cell delay = 1.905 ns ( 60.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.254 ns ( 39.70 % ) " "Info: Total interconnect delay = 1.254 ns ( 39.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "3.159 ns" { clk clk~clkctrl rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.159 ns" { clk clk~combout clk~clkctrl rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7] } { 0.000ns 0.000ns 0.139ns 1.115ns } { 0.000ns 1.090ns 0.000ns 0.815ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.179 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 3.179 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { clk } "NODE_NAME" } "" } } { "sine.vhd" "" { Text "D:/quartus/myproject/正弦信号发生器/sine.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G3 20 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G3; Fanout = 20; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "sine.vhd" "" { Text "D:/quartus/myproject/正弦信号发生器/sine.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.115 ns) + CELL(0.835 ns) 3.179 ns rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|altsyncram_b192:altsyncram1\|ram_block3a0~porta_address_reg0 3 MEM M4K_X52_Y21 8 " "Info: 3: + IC(1.115 ns) + CELL(0.835 ns) = 3.179 ns; Loc. = M4K_X52_Y21; Fanout = 8; MEM Node = 'rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|altsyncram_b192:altsyncram1\|ram_block3a0~porta_address_reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "1.950 ns" { clk~clkctrl rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_b192.tdf" "" { Text "D:/quartus/myproject/正弦信号发生器/db/altsyncram_b192.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.925 ns ( 60.55 % ) " "Info: Total cell delay = 1.925 ns ( 60.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.254 ns ( 39.45 % ) " "Info: Total interconnect delay = 1.254 ns ( 39.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "3.179 ns" { clk clk~clkctrl rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.179 ns" { clk clk~combout clk~clkctrl rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 } { 0.000ns 0.000ns 0.139ns 1.115ns } { 0.000ns 1.090ns 0.000ns 0.835ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "3.159 ns" { clk clk~clkctrl rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.159 ns" { clk clk~combout clk~clkctrl rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7] } { 0.000ns 0.000ns 0.139ns 1.115ns } { 0.000ns 1.090ns 0.000ns 0.815ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "3.179 ns" { clk clk~clkctrl rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.179 ns" { clk clk~combout clk~clkctrl rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 } { 0.000ns 0.000ns 0.139ns 1.115ns } { 0.000ns 1.090ns 0.000ns 0.835ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_b192.tdf" "" { Text "D:/quartus/myproject/正弦信号发生器/db/altsyncram_b192.tdf" 48 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_b192.tdf" "" { Text "D:/quartus/myproject/正弦信号发生器/db/altsyncram_b192.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "3.641 ns" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.641 ns" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7] } { 0.000ns 0.000ns } { 0.000ns 3.641ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "3.159 ns" { clk clk~clkctrl rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.159 ns" { clk clk~combout clk~clkctrl rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7] } { 0.000ns 0.000ns 0.139ns 1.115ns } { 0.000ns 1.090ns 0.000ns 0.815ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "3.179 ns" { clk clk~clkctrl rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.179 ns" { clk clk~combout clk~clkctrl rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ram_block3a0~porta_address_reg0 } { 0.000ns 0.000ns 0.139ns 1.115ns } { 0.000ns 1.090ns 0.000ns 0.835ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7] } { 0.000ns } { 0.109ns } } } { "db/altsyncram_b192.tdf" "" { Text "D:/quartus/myproject/正弦信号发生器/db/altsyncram_b192.tdf" 43 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\] register sld_hub:sld_hub_inst\|hub_tdo 86.07 MHz 11.618 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 86.07 MHz between source register \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 11.618 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.546 ns + Longest register register " "Info: + Longest register to register delay is 5.546 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\] 1 REG LCFF_X42_Y20_N25 29 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X42_Y20_N25; Fanout = 29; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1035 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.256 ns) + CELL(0.206 ns) 2.462 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~13 2 COMB LCCOMB_X47_Y21_N2 2 " "Info: 2: + IC(2.256 ns) + CELL(0.206 ns) = 2.462 ns; Loc. = LCCOMB_X47_Y21_N2; Fanout = 2; COMB Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~13'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "2.462 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1020 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.383 ns) + CELL(0.624 ns) 3.469 ns sld_hub:sld_hub_inst\|hub_tdo~562 3 COMB LCCOMB_X47_Y21_N20 1 " "Info: 3: + IC(0.383 ns) + CELL(0.624 ns) = 3.469 ns; Loc. = LCCOMB_X47_Y21_N20; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~562'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "1.007 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~562 } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.399 ns) + CELL(0.651 ns) 4.519 ns sld_hub:sld_hub_inst\|hub_tdo~565 4 COMB LCCOMB_X47_Y21_N4 1 " "Info: 4: + IC(0.399 ns) + CELL(0.651 ns) = 4.519 ns; Loc. = LCCOMB_X47_Y21_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~565'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "1.050 ns" { sld_hub:sld_hub_inst|hub_tdo~562 sld_hub:sld_hub_inst|hub_tdo~565 } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.375 ns) + CELL(0.544 ns) 5.438 ns sld_hub:sld_hub_inst\|hub_tdo~568 5 COMB LCCOMB_X47_Y21_N0 1 " "Info: 5: + IC(0.375 ns) + CELL(0.544 ns) = 5.438 ns; Loc. = LCCOMB_X47_Y21_N0; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~568'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "0.919 ns" { sld_hub:sld_hub_inst|hub_tdo~565 sld_hub:sld_hub_inst|hub_tdo~568 } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 5.546 ns sld_hub:sld_hub_inst\|hub_tdo 6 REG LCFF_X47_Y21_N1 2 " "Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 5.546 ns; Loc. = LCFF_X47_Y21_N1; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "0.108 ns" { sld_hub:sld_hub_inst|hub_tdo~568 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.133 ns ( 38.46 % ) " "Info: Total cell delay = 2.133 ns ( 38.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.413 ns ( 61.54 % ) " "Info: Total interconnect delay = 3.413 ns ( 61.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "5.546 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~562 sld_hub:sld_hub_inst|hub_tdo~565 sld_hub:sld_hub_inst|hub_tdo~568 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.546 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~562 sld_hub:sld_hub_inst|hub_tdo~565 sld_hub:sld_hub_inst|hub_tdo~568 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 2.256ns 0.383ns 0.399ns 0.375ns 0.000ns } { 0.000ns 0.206ns 0.624ns 0.651ns 0.544ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.001 ns - Smallest " "Info: - Smallest clock skew is 0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 3.628 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 3.628 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.766 ns) + CELL(0.000 ns) 1.766 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 126 " "Info: 2: + IC(1.766 ns) + CELL(0.000 ns) = 1.766 ns; Loc. = CLKCTRL_G0; Fanout = 126; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "1.766 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.196 ns) + CELL(0.666 ns) 3.628 ns sld_hub:sld_hub_inst\|hub_tdo 3 REG LCFF_X47_Y21_N1 2 " "Info: 3: + IC(1.196 ns) + CELL(0.666 ns) = 3.628 ns; Loc. = LCFF_X47_Y21_N1; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "1.862 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 18.36 % ) " "Info: Total cell delay = 0.666 ns ( 18.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.962 ns ( 81.64 % ) " "Info: Total interconnect delay = 2.962 ns ( 81.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "3.628 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.628 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.766ns 1.196ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 3.627 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 3.627 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.766 ns) + CELL(0.000 ns) 1.766 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 126 " "Info: 2: + IC(1.766 ns) + CELL(0.000 ns) = 1.766 ns; Loc. = CLKCTRL_G0; Fanout = 126; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "1.766 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.195 ns) + CELL(0.666 ns) 3.627 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\] 3 REG LCFF_X42_Y20_N25 29 " "Info: 3: + IC(1.195 ns) + CELL(0.666 ns) = 3.627 ns; Loc. = LCFF_X42_Y20_N25; Fanout = 29; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "1.861 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1035 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 18.36 % ) " "Info: Total cell delay = 0.666 ns ( 18.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.961 ns ( 81.64 % ) " "Info: Total interconnect delay = 2.961 ns ( 81.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "3.627 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.627 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } { 0.000ns 1.766ns 1.195ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "3.628 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.628 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.766ns 1.196ns } { 0.000ns 0.000ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "3.627 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.627 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } { 0.000ns 1.766ns 1.195ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1035 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1035 -1 0 } } { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "5.546 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~562 sld_hub:sld_hub_inst|hub_tdo~565 sld_hub:sld_hub_inst|hub_tdo~568 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.546 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~562 sld_hub:sld_hub_inst|hub_tdo~565 sld_hub:sld_hub_inst|hub_tdo~568 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 2.256ns 0.383ns 0.399ns 0.375ns 0.000ns } { 0.000ns 0.206ns 0.624ns 0.651ns 0.544ns 0.108ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "3.628 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.628 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.766ns 1.196ns } { 0.000ns 0.000ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "3.627 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.627 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } { 0.000ns 1.766ns 1.195ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}