sine.map.qmsg

原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 11 23:03:06 2008 " "Info: Processing started: Tue Nov 11 23:03:06 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sine -c sine " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sine -c sine" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rom1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom1-SYN " "Info: Found design unit 1: rom1-SYN" {  } { { "rom1.vhd" "" { Text "D:/quartus/myproject/正弦信号发生器/rom1.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rom1 " "Info: Found entity 1: rom1" {  } { { "rom1.vhd" "" { Text "D:/quartus/myproject/正弦信号发生器/rom1.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sine.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sine.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sine-beh " "Info: Found design unit 1: sine-beh" {  } { { "sine.vhd" "" { Text "D:/quartus/myproject/正弦信号发生器/sine.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sine " "Info: Found entity 1: sine" {  } { { "sine.vhd" "" { Text "D:/quartus/myproject/正弦信号发生器/sine.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "sine " "Info: Elaborating entity \"sine\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom1 rom1:u1 " "Info: Elaborating entity \"rom1\" for hierarchy \"rom1:u1\"" {  } { { "sine.vhd" "u1" { Text "D:/quartus/myproject/正弦信号发生器/sine.vhd" 27 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom1:u1\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"rom1:u1\|altsyncram:altsyncram_component\"" {  } { { "rom1.vhd" "altsyncram_component" { Text "D:/quartus/myproject/正弦信号发生器/rom1.vhd" 81 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4d51.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_4d51.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4d51 " "Info: Found entity 1: altsyncram_4d51" {  } { { "db/altsyncram_4d51.tdf" "" { Text "D:/quartus/myproject/正弦信号发生器/db/altsyncram_4d51.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4d51 rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated " "Info: Elaborating entity \"altsyncram_4d51\" for hierarchy \"rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_b192.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_b192.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_b192 " "Info: Found entity 1: altsyncram_b192" {  } { { "db/altsyncram_b192.tdf" "" { Text "D:/quartus/myproject/正弦信号发生器/db/altsyncram_b192.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_b192 rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|altsyncram_b192:altsyncram1 " "Info: Elaborating entity \"altsyncram_b192\" for hierarchy \"rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|altsyncram_b192:altsyncram1\"" {  } { { "db/altsyncram_4d51.tdf" "altsyncram1" { Text "D:/quartus/myproject/正弦信号发生器/db/altsyncram_4d51.tdf" 34 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_mod_ram_rom_pack " "Info: Found design unit 1: sld_mod_ram_rom_pack" {  } { { "c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 4 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_mod_ram_rom-rtl " "Info: Found design unit 2: sld_mod_ram_rom-rtl" {  } { { "c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 72 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_mod_ram_rom " "Info: Found entity 1: sld_mod_ram_rom" {  } { { "c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 16 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}