sine.fit.qmsg

原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成

{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_PRELIMINARY_TIMING" "EP2C35F484C8 " "Warning: Timing characteristics of device EP2C35F484C8 are preliminary" {  } {  } 0 0 "Timing characteristics of device %1!s! are preliminary" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "dout\[0\] 0 " "Warning: Pin \"dout\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "dout\[1\] 0 " "Warning: Pin \"dout\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "dout\[2\] 0 " "Warning: Pin \"dout\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "dout\[3\] 0 " "Warning: Pin \"dout\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "dout\[4\] 0 " "Warning: Pin \"dout\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "dout\[5\] 0 " "Warning: Pin \"dout\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "dout\[6\] 0 " "Warning: Pin \"dout\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "dout\[7\] 0 " "Warning: Pin \"dout\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|CLRN_SIGNAL~clkctrl " "Info: Node sld_hub:sld_hub_inst\|CLRN_SIGNAL~clkctrl uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[4\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[4\] -- routed using non-global resources" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[4\]" } } } } { "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[4] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[3\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[3\] -- routed using non-global resources" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[3\]" } } } } { "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[1\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[1\] -- routed using non-global resources" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[1\]" } } } } { "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[0\] -- routed using non-global resources" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[0\]" } } } } { "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[2\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[2\] -- routed using non-global resources" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[2\]" } } } } { "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { sld_hub:sld_hub_inst|CLRN_SIGNAL~clkctrl } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|CLRN_SIGNAL~clkctrl" } } } } { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 307 -1 0 } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { sld_hub:sld_hub_inst|CLRN_SIGNAL~clkctrl } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]~clkctrl " "Info: Node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]~clkctrl uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\] " "Info: Port clear -- assigned as a global for destination node rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\] -- routed using non-global resources" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]" } } } } { "c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[1\] " "Info: Port clear -- assigned as a global for destination node rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[1\] -- routed using non-global resources" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[1\]" } } } } { "c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[2\] " "Info: Port clear -- assigned as a global for destination node rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[2\] -- routed using non-global resources" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[2\]" } } } } { "c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[3\] " "Info: Port clear -- assigned as a global for destination node rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[3\] -- routed using non-global resources" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[3\]" } } } } { "c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } } { "D:/quartus/m