sine.fit.qmsg

原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成

{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN M1 (CLK2, LVDSCLK1p, Input)) " "Info: Automatically promoted node clk (placed in PIN M1 (CLK2, LVDSCLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "sine.vhd" "" { Text "D:/quartus/myproject/正弦信号发生器/sine.vhd" 7 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { clk } "NODE_NAME" } "" } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP  " "Info: Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|CLRN_SIGNAL  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|CLRN_SIGNAL " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 307 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|CLRN_SIGNAL" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { sld_hub:sld_hub_inst|CLRN_SIGNAL } "NODE_NAME" } "" } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { sld_hub:sld_hub_inst|CLRN_SIGNAL } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~474 " "Info: Destination node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~474" {  } { { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1020 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~474" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~474 } "NODE_NAME" } "" } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~474 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~5 " "Info: Destination node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~5" {  } { { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1020 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~5" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5 } "NODE_NAME" } "" } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1035 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } "" } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|hub_tdo~566 " "Info: Destination node sld_hub:sld_hub_inst\|hub_tdo~566" {  } { { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|hub_tdo~566" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { sld_hub:sld_hub_inst|hub_tdo~566 } "NODE_NAME" } "" } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { sld_hub:sld_hub_inst|hub_tdo~566 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|hub_tdo~567 " "Info: Destination node sld_hub:sld_hub_inst\|hub_tdo~567" {  } { { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|hub_tdo~567" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { sld_hub:sld_hub_inst|hub_tdo~567 } "NODE_NAME" } "" } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { sld_hub:sld_hub_inst|hub_tdo~567 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0 " "Info: Destination node rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0 } "NODE_NAME" } "" } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg~6 " "Info: Destination node rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg~6" {  } { { "c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 708 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg~6" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg~6 } "NODE_NAME" } "" } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg~6 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] } "NODE_NAME" } "" } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0  " "Info: Automatically promoted node rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0 } "NODE_NAME" } "" } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\]  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process1~1 " "Info: Destination node rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process1~1" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process1~1" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|process1~1 } "NODE_NAME" } "" } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|process1~1 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process0~11 " "Info: Destination node rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process0~11" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process0~11" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|process0~11 } "NODE_NAME" } "" } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|process0~11 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~13 " "Info: Destination node rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~13" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rom1:u1\|altsyncram:altsyncram_component\|altsyncram_4d51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~13" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~13 } "NODE_NAME" } "" } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~13 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sine" "UNKNOWN" "V1" "D:/quartus/myproject/正弦信号发生器/db/sine.quartus_db" { Floorplan "D:/quartus/myproject/正弦信号发生器/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } "" } } { "D:/quartus/myproject/正弦信号发生器/sine.fld" "" { Floorplan "D:/quartus/myproject/正弦信号发生器/sine.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}