sine.map.eqn

原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成

M1_q_b[5]_clock_1 = A1L5;
M1_q_b[5]_PORT_B_data_out = MEMORY(M1_q_b[5]_PORT_A_data_in_reg, M1_q_b[5]_PORT_B_data_in_reg, M1_q_b[5]_PORT_A_address_reg, M1_q_b[5]_PORT_B_address_reg, M1_q_b[5]_PORT_A_write_enable_reg, M1_q_b[5]_PORT_B_write_enable_reg, , , M1_q_b[5]_clock_0, M1_q_b[5]_clock_1, , , , );
M1_q_b[5] = M1_q_b[5]_PORT_B_data_out[0];


--M1_q_a[6] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_a[6]_PORT_A_data_in = VCC;
M1_q_a[6]_PORT_A_data_in_reg = DFFE(M1_q_a[6]_PORT_A_data_in, M1_q_a[6]_clock_0, , , );
M1_q_a[6]_PORT_B_data_in = N1_ram_rom_data_reg[6];
M1_q_a[6]_PORT_B_data_in_reg = DFFE(M1_q_a[6]_PORT_B_data_in, M1_q_a[6]_clock_1, , , );
M1_q_a[6]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_a[6]_PORT_A_address_reg = DFFE(M1_q_a[6]_PORT_A_address, M1_q_a[6]_clock_0, , , );
M1_q_a[6]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_a[6]_PORT_B_address_reg = DFFE(M1_q_a[6]_PORT_B_address, M1_q_a[6]_clock_1, , , );
M1_q_a[6]_PORT_A_write_enable = GND;
M1_q_a[6]_PORT_A_write_enable_reg = DFFE(M1_q_a[6]_PORT_A_write_enable, M1_q_a[6]_clock_0, , , );
M1_q_a[6]_PORT_B_write_enable = N1L3;
M1_q_a[6]_PORT_B_write_enable_reg = DFFE(M1_q_a[6]_PORT_B_write_enable, M1_q_a[6]_clock_1, , , );
M1_q_a[6]_clock_0 = clk;
M1_q_a[6]_clock_1 = A1L5;
M1_q_a[6]_PORT_A_data_out = MEMORY(M1_q_a[6]_PORT_A_data_in_reg, M1_q_a[6]_PORT_B_data_in_reg, M1_q_a[6]_PORT_A_address_reg, M1_q_a[6]_PORT_B_address_reg, M1_q_a[6]_PORT_A_write_enable_reg, M1_q_a[6]_PORT_B_write_enable_reg, , , M1_q_a[6]_clock_0, M1_q_a[6]_clock_1, , , , );
M1_q_a[6]_PORT_A_data_out_reg = DFFE(M1_q_a[6]_PORT_A_data_out, M1_q_a[6]_clock_0, , , );
M1_q_a[6] = M1_q_a[6]_PORT_A_data_out_reg[0];

--M1_q_b[6] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_b[6]
M1_q_b[6]_PORT_A_data_in = VCC;
M1_q_b[6]_PORT_A_data_in_reg = DFFE(M1_q_b[6]_PORT_A_data_in, M1_q_b[6]_clock_0, , , );
M1_q_b[6]_PORT_B_data_in = N1_ram_rom_data_reg[6];
M1_q_b[6]_PORT_B_data_in_reg = DFFE(M1_q_b[6]_PORT_B_data_in, M1_q_b[6]_clock_1, , , );
M1_q_b[6]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_b[6]_PORT_A_address_reg = DFFE(M1_q_b[6]_PORT_A_address, M1_q_b[6]_clock_0, , , );
M1_q_b[6]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_b[6]_PORT_B_address_reg = DFFE(M1_q_b[6]_PORT_B_address, M1_q_b[6]_clock_1, , , );
M1_q_b[6]_PORT_A_write_enable = GND;
M1_q_b[6]_PORT_A_write_enable_reg = DFFE(M1_q_b[6]_PORT_A_write_enable, M1_q_b[6]_clock_0, , , );
M1_q_b[6]_PORT_B_write_enable = N1L3;
M1_q_b[6]_PORT_B_write_enable_reg = DFFE(M1_q_b[6]_PORT_B_write_enable, M1_q_b[6]_clock_1, , , );
M1_q_b[6]_clock_0 = clk;
M1_q_b[6]_clock_1 = A1L5;
M1_q_b[6]_PORT_B_data_out = MEMORY(M1_q_b[6]_PORT_A_data_in_reg, M1_q_b[6]_PORT_B_data_in_reg, M1_q_b[6]_PORT_A_address_reg, M1_q_b[6]_PORT_B_address_reg, M1_q_b[6]_PORT_A_write_enable_reg, M1_q_b[6]_PORT_B_write_enable_reg, , , M1_q_b[6]_clock_0, M1_q_b[6]_clock_1, , , , );
M1_q_b[6] = M1_q_b[6]_PORT_B_data_out[0];


--M1_q_a[7] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_a[7]_PORT_A_data_in = VCC;
M1_q_a[7]_PORT_A_data_in_reg = DFFE(M1_q_a[7]_PORT_A_data_in, M1_q_a[7]_clock_0, , , );
M1_q_a[7]_PORT_B_data_in = N1_ram_rom_data_reg[7];
M1_q_a[7]_PORT_B_data_in_reg = DFFE(M1_q_a[7]_PORT_B_data_in, M1_q_a[7]_clock_1, , , );
M1_q_a[7]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_a[7]_PORT_A_address_reg = DFFE(M1_q_a[7]_PORT_A_address, M1_q_a[7]_clock_0, , , );
M1_q_a[7]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_a[7]_PORT_B_address_reg = DFFE(M1_q_a[7]_PORT_B_address, M1_q_a[7]_clock_1, , , );
M1_q_a[7]_PORT_A_write_enable = GND;
M1_q_a[7]_PORT_A_write_enable_reg = DFFE(M1_q_a[7]_PORT_A_write_enable, M1_q_a[7]_clock_0, , , );
M1_q_a[7]_PORT_B_write_enable = N1L3;
M1_q_a[7]_PORT_B_write_enable_reg = DFFE(M1_q_a[7]_PORT_B_write_enable, M1_q_a[7]_clock_1, , , );
M1_q_a[7]_clock_0 = clk;
M1_q_a[7]_clock_1 = A1L5;
M1_q_a[7]_PORT_A_data_out = MEMORY(M1_q_a[7]_PORT_A_data_in_reg, M1_q_a[7]_PORT_B_data_in_reg, M1_q_a[7]_PORT_A_address_reg, M1_q_a[7]_PORT_B_address_reg, M1_q_a[7]_PORT_A_write_enable_reg, M1_q_a[7]_PORT_B_write_enable_reg, , , M1_q_a[7]_clock_0, M1_q_a[7]_clock_1, , , , );
M1_q_a[7]_PORT_A_data_out_reg = DFFE(M1_q_a[7]_PORT_A_data_out, M1_q_a[7]_clock_0, , , );
M1_q_a[7] = M1_q_a[7]_PORT_A_data_out_reg[0];

--M1_q_b[7] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_b[7]
M1_q_b[7]_PORT_A_data_in = VCC;
M1_q_b[7]_PORT_A_data_in_reg = DFFE(M1_q_b[7]_PORT_A_data_in, M1_q_b[7]_clock_0, , , );
M1_q_b[7]_PORT_B_data_in = N1_ram_rom_data_reg[7];
M1_q_b[7]_PORT_B_data_in_reg = DFFE(M1_q_b[7]_PORT_B_data_in, M1_q_b[7]_clock_1, , , );
M1_q_b[7]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_b[7]_PORT_A_address_reg = DFFE(M1_q_b[7]_PORT_A_address, M1_q_b[7]_clock_0, , , );
M1_q_b[7]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_b[7]_PORT_B_address_reg = DFFE(M1_q_b[7]_PORT_B_address, M1_q_b[7]_clock_1, , , );
M1_q_b[7]_PORT_A_write_enable = GND;
M1_q_b[7]_PORT_A_write_enable_reg = DFFE(M1_q_b[7]_PORT_A_write_enable, M1_q_b[7]_clock_0, , , );
M1_q_b[7]_PORT_B_write_enable = N1L3;
M1_q_b[7]_PORT_B_write_enable_reg = DFFE(M1_q_b[7]_PORT_B_write_enable, M1_q_b[7]_clock_1, , , );
M1_q_b[7]_clock_0 = clk;
M1_q_b[7]_clock_1 = A1L5;
M1_q_b[7]_PORT_B_data_out = MEMORY(M1_q_b[7]_PORT_A_data_in_reg, M1_q_b[7]_PORT_B_data_in_reg, M1_q_b[7]_PORT_A_address_reg, M1_q_b[7]_PORT_B_address_reg, M1_q_b[7]_PORT_A_write_enable_reg, M1_q_b[7]_PORT_B_write_enable_reg, , , M1_q_b[7]_clock_0, M1_q_b[7]_clock_1, , , , );
M1_q_b[7] = M1_q_b[7]_PORT_B_data_out[0];


--A1L6 is altera_internal_jtag~TDO
A1L6 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , B1L18);

--A1L7 is altera_internal_jtag~TMSUTAP
A1L7 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , B1L18);

--A1L5 is altera_internal_jtag~TCKUTAP
A1L5 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , B1L18);

--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , B1L18);


--H1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]
H1_state[5] = AMPP_FUNCTION(A1L5, H1L22);


--D4_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]
D4_Q[2] = AMPP_FUNCTION(A1L5, B1L21, B1_CLRN_SIGNAL, B1L27);


--B1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode
B1_jtag_debug_mode = AMPP_FUNCTION(A1L5, B1L38, H1_state[0]);


--D6_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]
D6_Q[0] = AMPP_FUNCTION(A1L5, altera_internal_jtag, B1_CLRN_SIGNAL, B1L24);


--B1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1
B1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L5, A1L43, H1_state[0], H1_state[12]);


--D2_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]
D2_Q[0] = AMPP_FUNCTION(A1L5, D2L4, B1_CLRN_SIGNAL);


--N1L11 is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|name_gen~33
N1L11 = AMPP_FUNCTION(B1_jtag_debug_mode, D6_Q[0], B1_jtag_debug_mode_usr1, D2_Q[0]);


--N1L3 is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|enable_write~11
N1L3 = AMPP_FUNCTION(H1_state[5], D4_Q[2], N1L11);


--q1[0] is q1[0]
q1[0] = DFFEAS(A1L26, clk,  ,  ,  ,  ,  ,  ,  );


--q1[1] is q1[1]
q1[1] = DFFEAS(A1L29, clk,  ,  ,  ,  ,  ,  ,  );


--q1[2] is q1[2]
q1[2] = DFFEAS(A1L32, clk,  ,  ,  ,  ,  ,  ,  );


--q1[3] is q1[3]
q1[3] = DFFEAS(A1L35, clk,  ,  ,  ,  ,  ,  ,  );


--q1[4] is q1[4]
q1[4] = DFFEAS(A1L38, clk,  ,  ,  ,  ,  ,  ,  );


--q1[5] is q1[5]
q1[5] = DFFEAS(A1L41, clk,  ,  ,  ,  ,  ,  ,  );


--N1_ram_rom_data_reg[0] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]
N1_ram_rom_data_reg[0] = AMPP_FUNCTION(A1L5, N1L46, N1L45);


--N1_ram_rom_addr_reg[0] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]
N1_ram_rom_addr_reg[0] = AMPP_FUNCTION(A1L5, N1L19, N1_ram_rom_addr_reg[1], !D4_Q[0], N1L12);


--N1_ram_rom_addr_reg[1] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]
N1_ram_rom_addr_reg[1] = AMPP_FUNCTION(A1L5, N1L22, N1_ram_rom_addr_reg[2], !D4_Q[0], N1L12);


--N1_ram_rom_addr_reg[2] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]
N1_ram_rom_addr_reg[2] = AMPP_FUNCTION(A1L5, N1L25, N1_ram_rom_addr_reg[3], !D4_Q[0], N1L12);


--N1_ram_rom_addr_reg[3] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]
N1_ram_rom_addr_reg[3] = AMPP_FUNCTION(A1L5, N1L28, N1_ram_rom_addr_reg[4], !D4_Q[0], N1L12);


--N1_ram_rom_addr_reg[4] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]
N1_ram_rom_addr_reg[4] = AMPP_FUNCTION(A1L5, N1L31, N1_ram_rom_addr_reg[5], !D4_Q[0], N1L12);


--N1_ram_rom_addr_reg[5] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]
N1_ram_rom_addr_reg[5] = AMPP_FUNCTION(A1L5, N1L34, altera_internal_jtag, !D4_Q[0], N1L12);


--N1_ram_rom_data_reg[1] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]
N1_ram_rom_data_reg[1] = AMPP_FUNCTION(A1L5, N1L47, N1L45);


--N1_ram_rom_data_reg[2] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]
N1_ram_rom_data_reg[2] = AMPP_FUNCTION(A1L5, N1L48, N1L45);


--N1_ram_rom_data_reg[3] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]
N1_ram_rom_data_reg[3] = AMPP_FUNCTION(A1L5, N1L49, N1L45);


--N1_ram_rom_data_reg[4] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]
N1_ram_rom_data_reg[4] = AMPP_FUNCTION(A1L5, N1L50, N1L45);


--N1_ram_rom_data_reg[5] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]
N1_ram_rom_data_reg[5] = AMPP_FUNCTION(A1L5, N1L51, N1L45);


--N1_ram_rom_data_reg[6] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]
N1_ram_rom_data_reg[6] = AMPP_FUNCTION(A1L5, N1L52, N1L45);


--N1_ram_rom_data_reg[7] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]
N1_ram_rom_data_reg[7] = AMPP_FUNCTION(A1L5, N1L53, N1L45);


--B1_hub_tdo is sld_hub:sld_hub_inst|hub_tdo
B1_hub_tdo = AMPP_FUNCTION(!A1L5, B1L16, !H1_state[8]);


--H1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3]
H1_state[3] = AMPP_FUNCTION(A1L5, H1L19);


--H1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4]
H1_state[4] = AMPP_FUNCTION(A1L5, H1L20, A1L7);


--H1L22 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~14
H1L22 = AMPP_FUNCTION(A1L7, H1_state[3], H1_state[4]);


--D5_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[2]
D5_Q[2] = AMPP_FUNCTION(A1L5, D3_Q[2], B1_CLRN_SIGNAL, B1L5);


--D3_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2]
D3_Q[2] = AMPP_FUNCTION(A1L5, B1L30, B1_CLRN_SIGNAL, D3L4);


--B1L21 is sld_hub:sld_hub_inst|IRF_D[1][2]~45
B1L21 = AMPP_FUNCTION(D5_Q[2], D3_Q[2], D2_Q[0]);


--B1_CLRN_SIGNAL is sld_hub:sld_hub_inst|CLRN_SIGNAL
B1_CLRN_SIGNAL = AMPP_FUNCTION(A1L5, B1L2);


--B1_OK_TO_UPDATE_IR_Q is sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q
B1_OK_TO_UPDATE_IR_Q = AMPP_FUNCTION(A1L5, B1L41);


--B1L6 is sld_hub:sld_hub_inst|GEN_SHADOW_IRF~9
B1L6 = AMPP_FUNCTION(H1_state[5], B1_OK_TO_UPDATE_IR_Q);


--D7_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]
D7_Q[0] = AMPP_FUNCTION(A1L5, D7L3, B1L24);


--J1_dffe1a[2] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|dffe1a[2]
J1_dffe1a[2] = AMPP_FUNCTION(A1L5, J1_w_anode28w[3], B1_CLRN_SIGNAL, B1L4);