sine.map.eqn

原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--M1_q_a[0] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_a[0]_PORT_A_data_in = VCC;
M1_q_a[0]_PORT_A_data_in_reg = DFFE(M1_q_a[0]_PORT_A_data_in, M1_q_a[0]_clock_0, , , );
M1_q_a[0]_PORT_B_data_in = N1_ram_rom_data_reg[0];
M1_q_a[0]_PORT_B_data_in_reg = DFFE(M1_q_a[0]_PORT_B_data_in, M1_q_a[0]_clock_1, , , );
M1_q_a[0]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_a[0]_PORT_A_address_reg = DFFE(M1_q_a[0]_PORT_A_address, M1_q_a[0]_clock_0, , , );
M1_q_a[0]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_a[0]_PORT_B_address_reg = DFFE(M1_q_a[0]_PORT_B_address, M1_q_a[0]_clock_1, , , );
M1_q_a[0]_PORT_A_write_enable = GND;
M1_q_a[0]_PORT_A_write_enable_reg = DFFE(M1_q_a[0]_PORT_A_write_enable, M1_q_a[0]_clock_0, , , );
M1_q_a[0]_PORT_B_write_enable = N1L3;
M1_q_a[0]_PORT_B_write_enable_reg = DFFE(M1_q_a[0]_PORT_B_write_enable, M1_q_a[0]_clock_1, , , );
M1_q_a[0]_clock_0 = clk;
M1_q_a[0]_clock_1 = A1L5;
M1_q_a[0]_PORT_A_data_out = MEMORY(M1_q_a[0]_PORT_A_data_in_reg, M1_q_a[0]_PORT_B_data_in_reg, M1_q_a[0]_PORT_A_address_reg, M1_q_a[0]_PORT_B_address_reg, M1_q_a[0]_PORT_A_write_enable_reg, M1_q_a[0]_PORT_B_write_enable_reg, , , M1_q_a[0]_clock_0, M1_q_a[0]_clock_1, , , , );
M1_q_a[0]_PORT_A_data_out_reg = DFFE(M1_q_a[0]_PORT_A_data_out, M1_q_a[0]_clock_0, , , );
M1_q_a[0] = M1_q_a[0]_PORT_A_data_out_reg[0];

--M1_q_b[0] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_b[0]
M1_q_b[0]_PORT_A_data_in = VCC;
M1_q_b[0]_PORT_A_data_in_reg = DFFE(M1_q_b[0]_PORT_A_data_in, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_data_in = N1_ram_rom_data_reg[0];
M1_q_b[0]_PORT_B_data_in_reg = DFFE(M1_q_b[0]_PORT_B_data_in, M1_q_b[0]_clock_1, , , );
M1_q_b[0]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_b[0]_PORT_A_address_reg = DFFE(M1_q_b[0]_PORT_A_address, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_b[0]_PORT_B_address_reg = DFFE(M1_q_b[0]_PORT_B_address, M1_q_b[0]_clock_1, , , );
M1_q_b[0]_PORT_A_write_enable = GND;
M1_q_b[0]_PORT_A_write_enable_reg = DFFE(M1_q_b[0]_PORT_A_write_enable, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_write_enable = N1L3;
M1_q_b[0]_PORT_B_write_enable_reg = DFFE(M1_q_b[0]_PORT_B_write_enable, M1_q_b[0]_clock_1, , , );
M1_q_b[0]_clock_0 = clk;
M1_q_b[0]_clock_1 = A1L5;
M1_q_b[0]_PORT_B_data_out = MEMORY(M1_q_b[0]_PORT_A_data_in_reg, M1_q_b[0]_PORT_B_data_in_reg, M1_q_b[0]_PORT_A_address_reg, M1_q_b[0]_PORT_B_address_reg, M1_q_b[0]_PORT_A_write_enable_reg, M1_q_b[0]_PORT_B_write_enable_reg, , , M1_q_b[0]_clock_0, M1_q_b[0]_clock_1, , , , );
M1_q_b[0] = M1_q_b[0]_PORT_B_data_out[0];


--M1_q_a[1] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_a[1]_PORT_A_data_in = VCC;
M1_q_a[1]_PORT_A_data_in_reg = DFFE(M1_q_a[1]_PORT_A_data_in, M1_q_a[1]_clock_0, , , );
M1_q_a[1]_PORT_B_data_in = N1_ram_rom_data_reg[1];
M1_q_a[1]_PORT_B_data_in_reg = DFFE(M1_q_a[1]_PORT_B_data_in, M1_q_a[1]_clock_1, , , );
M1_q_a[1]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_a[1]_PORT_A_address_reg = DFFE(M1_q_a[1]_PORT_A_address, M1_q_a[1]_clock_0, , , );
M1_q_a[1]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_a[1]_PORT_B_address_reg = DFFE(M1_q_a[1]_PORT_B_address, M1_q_a[1]_clock_1, , , );
M1_q_a[1]_PORT_A_write_enable = GND;
M1_q_a[1]_PORT_A_write_enable_reg = DFFE(M1_q_a[1]_PORT_A_write_enable, M1_q_a[1]_clock_0, , , );
M1_q_a[1]_PORT_B_write_enable = N1L3;
M1_q_a[1]_PORT_B_write_enable_reg = DFFE(M1_q_a[1]_PORT_B_write_enable, M1_q_a[1]_clock_1, , , );
M1_q_a[1]_clock_0 = clk;
M1_q_a[1]_clock_1 = A1L5;
M1_q_a[1]_PORT_A_data_out = MEMORY(M1_q_a[1]_PORT_A_data_in_reg, M1_q_a[1]_PORT_B_data_in_reg, M1_q_a[1]_PORT_A_address_reg, M1_q_a[1]_PORT_B_address_reg, M1_q_a[1]_PORT_A_write_enable_reg, M1_q_a[1]_PORT_B_write_enable_reg, , , M1_q_a[1]_clock_0, M1_q_a[1]_clock_1, , , , );
M1_q_a[1]_PORT_A_data_out_reg = DFFE(M1_q_a[1]_PORT_A_data_out, M1_q_a[1]_clock_0, , , );
M1_q_a[1] = M1_q_a[1]_PORT_A_data_out_reg[0];

--M1_q_b[1] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_b[1]
M1_q_b[1]_PORT_A_data_in = VCC;
M1_q_b[1]_PORT_A_data_in_reg = DFFE(M1_q_b[1]_PORT_A_data_in, M1_q_b[1]_clock_0, , , );
M1_q_b[1]_PORT_B_data_in = N1_ram_rom_data_reg[1];
M1_q_b[1]_PORT_B_data_in_reg = DFFE(M1_q_b[1]_PORT_B_data_in, M1_q_b[1]_clock_1, , , );
M1_q_b[1]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_b[1]_PORT_A_address_reg = DFFE(M1_q_b[1]_PORT_A_address, M1_q_b[1]_clock_0, , , );
M1_q_b[1]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_b[1]_PORT_B_address_reg = DFFE(M1_q_b[1]_PORT_B_address, M1_q_b[1]_clock_1, , , );
M1_q_b[1]_PORT_A_write_enable = GND;
M1_q_b[1]_PORT_A_write_enable_reg = DFFE(M1_q_b[1]_PORT_A_write_enable, M1_q_b[1]_clock_0, , , );
M1_q_b[1]_PORT_B_write_enable = N1L3;
M1_q_b[1]_PORT_B_write_enable_reg = DFFE(M1_q_b[1]_PORT_B_write_enable, M1_q_b[1]_clock_1, , , );
M1_q_b[1]_clock_0 = clk;
M1_q_b[1]_clock_1 = A1L5;
M1_q_b[1]_PORT_B_data_out = MEMORY(M1_q_b[1]_PORT_A_data_in_reg, M1_q_b[1]_PORT_B_data_in_reg, M1_q_b[1]_PORT_A_address_reg, M1_q_b[1]_PORT_B_address_reg, M1_q_b[1]_PORT_A_write_enable_reg, M1_q_b[1]_PORT_B_write_enable_reg, , , M1_q_b[1]_clock_0, M1_q_b[1]_clock_1, , , , );
M1_q_b[1] = M1_q_b[1]_PORT_B_data_out[0];


--M1_q_a[2] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_a[2]_PORT_A_data_in = VCC;
M1_q_a[2]_PORT_A_data_in_reg = DFFE(M1_q_a[2]_PORT_A_data_in, M1_q_a[2]_clock_0, , , );
M1_q_a[2]_PORT_B_data_in = N1_ram_rom_data_reg[2];
M1_q_a[2]_PORT_B_data_in_reg = DFFE(M1_q_a[2]_PORT_B_data_in, M1_q_a[2]_clock_1, , , );
M1_q_a[2]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_a[2]_PORT_A_address_reg = DFFE(M1_q_a[2]_PORT_A_address, M1_q_a[2]_clock_0, , , );
M1_q_a[2]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_a[2]_PORT_B_address_reg = DFFE(M1_q_a[2]_PORT_B_address, M1_q_a[2]_clock_1, , , );
M1_q_a[2]_PORT_A_write_enable = GND;
M1_q_a[2]_PORT_A_write_enable_reg = DFFE(M1_q_a[2]_PORT_A_write_enable, M1_q_a[2]_clock_0, , , );
M1_q_a[2]_PORT_B_write_enable = N1L3;
M1_q_a[2]_PORT_B_write_enable_reg = DFFE(M1_q_a[2]_PORT_B_write_enable, M1_q_a[2]_clock_1, , , );
M1_q_a[2]_clock_0 = clk;
M1_q_a[2]_clock_1 = A1L5;
M1_q_a[2]_PORT_A_data_out = MEMORY(M1_q_a[2]_PORT_A_data_in_reg, M1_q_a[2]_PORT_B_data_in_reg, M1_q_a[2]_PORT_A_address_reg, M1_q_a[2]_PORT_B_address_reg, M1_q_a[2]_PORT_A_write_enable_reg, M1_q_a[2]_PORT_B_write_enable_reg, , , M1_q_a[2]_clock_0, M1_q_a[2]_clock_1, , , , );
M1_q_a[2]_PORT_A_data_out_reg = DFFE(M1_q_a[2]_PORT_A_data_out, M1_q_a[2]_clock_0, , , );
M1_q_a[2] = M1_q_a[2]_PORT_A_data_out_reg[0];

--M1_q_b[2] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_b[2]
M1_q_b[2]_PORT_A_data_in = VCC;
M1_q_b[2]_PORT_A_data_in_reg = DFFE(M1_q_b[2]_PORT_A_data_in, M1_q_b[2]_clock_0, , , );
M1_q_b[2]_PORT_B_data_in = N1_ram_rom_data_reg[2];
M1_q_b[2]_PORT_B_data_in_reg = DFFE(M1_q_b[2]_PORT_B_data_in, M1_q_b[2]_clock_1, , , );
M1_q_b[2]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_b[2]_PORT_A_address_reg = DFFE(M1_q_b[2]_PORT_A_address, M1_q_b[2]_clock_0, , , );
M1_q_b[2]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_b[2]_PORT_B_address_reg = DFFE(M1_q_b[2]_PORT_B_address, M1_q_b[2]_clock_1, , , );
M1_q_b[2]_PORT_A_write_enable = GND;
M1_q_b[2]_PORT_A_write_enable_reg = DFFE(M1_q_b[2]_PORT_A_write_enable, M1_q_b[2]_clock_0, , , );
M1_q_b[2]_PORT_B_write_enable = N1L3;
M1_q_b[2]_PORT_B_write_enable_reg = DFFE(M1_q_b[2]_PORT_B_write_enable, M1_q_b[2]_clock_1, , , );
M1_q_b[2]_clock_0 = clk;
M1_q_b[2]_clock_1 = A1L5;
M1_q_b[2]_PORT_B_data_out = MEMORY(M1_q_b[2]_PORT_A_data_in_reg, M1_q_b[2]_PORT_B_data_in_reg, M1_q_b[2]_PORT_A_address_reg, M1_q_b[2]_PORT_B_address_reg, M1_q_b[2]_PORT_A_write_enable_reg, M1_q_b[2]_PORT_B_write_enable_reg, , , M1_q_b[2]_clock_0, M1_q_b[2]_clock_1, , , , );
M1_q_b[2] = M1_q_b[2]_PORT_B_data_out[0];


--M1_q_a[3] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_a[3]_PORT_A_data_in = VCC;
M1_q_a[3]_PORT_A_data_in_reg = DFFE(M1_q_a[3]_PORT_A_data_in, M1_q_a[3]_clock_0, , , );
M1_q_a[3]_PORT_B_data_in = N1_ram_rom_data_reg[3];
M1_q_a[3]_PORT_B_data_in_reg = DFFE(M1_q_a[3]_PORT_B_data_in, M1_q_a[3]_clock_1, , , );
M1_q_a[3]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_a[3]_PORT_A_address_reg = DFFE(M1_q_a[3]_PORT_A_address, M1_q_a[3]_clock_0, , , );
M1_q_a[3]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_a[3]_PORT_B_address_reg = DFFE(M1_q_a[3]_PORT_B_address, M1_q_a[3]_clock_1, , , );
M1_q_a[3]_PORT_A_write_enable = GND;
M1_q_a[3]_PORT_A_write_enable_reg = DFFE(M1_q_a[3]_PORT_A_write_enable, M1_q_a[3]_clock_0, , , );
M1_q_a[3]_PORT_B_write_enable = N1L3;
M1_q_a[3]_PORT_B_write_enable_reg = DFFE(M1_q_a[3]_PORT_B_write_enable, M1_q_a[3]_clock_1, , , );
M1_q_a[3]_clock_0 = clk;
M1_q_a[3]_clock_1 = A1L5;
M1_q_a[3]_PORT_A_data_out = MEMORY(M1_q_a[3]_PORT_A_data_in_reg, M1_q_a[3]_PORT_B_data_in_reg, M1_q_a[3]_PORT_A_address_reg, M1_q_a[3]_PORT_B_address_reg, M1_q_a[3]_PORT_A_write_enable_reg, M1_q_a[3]_PORT_B_write_enable_reg, , , M1_q_a[3]_clock_0, M1_q_a[3]_clock_1, , , , );
M1_q_a[3]_PORT_A_data_out_reg = DFFE(M1_q_a[3]_PORT_A_data_out, M1_q_a[3]_clock_0, , , );
M1_q_a[3] = M1_q_a[3]_PORT_A_data_out_reg[0];

--M1_q_b[3] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_b[3]
M1_q_b[3]_PORT_A_data_in = VCC;
M1_q_b[3]_PORT_A_data_in_reg = DFFE(M1_q_b[3]_PORT_A_data_in, M1_q_b[3]_clock_0, , , );
M1_q_b[3]_PORT_B_data_in = N1_ram_rom_data_reg[3];
M1_q_b[3]_PORT_B_data_in_reg = DFFE(M1_q_b[3]_PORT_B_data_in, M1_q_b[3]_clock_1, , , );
M1_q_b[3]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_b[3]_PORT_A_address_reg = DFFE(M1_q_b[3]_PORT_A_address, M1_q_b[3]_clock_0, , , );
M1_q_b[3]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_b[3]_PORT_B_address_reg = DFFE(M1_q_b[3]_PORT_B_address, M1_q_b[3]_clock_1, , , );
M1_q_b[3]_PORT_A_write_enable = GND;
M1_q_b[3]_PORT_A_write_enable_reg = DFFE(M1_q_b[3]_PORT_A_write_enable, M1_q_b[3]_clock_0, , , );
M1_q_b[3]_PORT_B_write_enable = N1L3;
M1_q_b[3]_PORT_B_write_enable_reg = DFFE(M1_q_b[3]_PORT_B_write_enable, M1_q_b[3]_clock_1, , , );
M1_q_b[3]_clock_0 = clk;
M1_q_b[3]_clock_1 = A1L5;
M1_q_b[3]_PORT_B_data_out = MEMORY(M1_q_b[3]_PORT_A_data_in_reg, M1_q_b[3]_PORT_B_data_in_reg, M1_q_b[3]_PORT_A_address_reg, M1_q_b[3]_PORT_B_address_reg, M1_q_b[3]_PORT_A_write_enable_reg, M1_q_b[3]_PORT_B_write_enable_reg, , , M1_q_b[3]_clock_0, M1_q_b[3]_clock_1, , , , );
M1_q_b[3] = M1_q_b[3]_PORT_B_data_out[0];


--M1_q_a[4] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_a[4]_PORT_A_data_in = VCC;
M1_q_a[4]_PORT_A_data_in_reg = DFFE(M1_q_a[4]_PORT_A_data_in, M1_q_a[4]_clock_0, , , );
M1_q_a[4]_PORT_B_data_in = N1_ram_rom_data_reg[4];
M1_q_a[4]_PORT_B_data_in_reg = DFFE(M1_q_a[4]_PORT_B_data_in, M1_q_a[4]_clock_1, , , );
M1_q_a[4]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_a[4]_PORT_A_address_reg = DFFE(M1_q_a[4]_PORT_A_address, M1_q_a[4]_clock_0, , , );
M1_q_a[4]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_a[4]_PORT_B_address_reg = DFFE(M1_q_a[4]_PORT_B_address, M1_q_a[4]_clock_1, , , );
M1_q_a[4]_PORT_A_write_enable = GND;
M1_q_a[4]_PORT_A_write_enable_reg = DFFE(M1_q_a[4]_PORT_A_write_enable, M1_q_a[4]_clock_0, , , );
M1_q_a[4]_PORT_B_write_enable = N1L3;
M1_q_a[4]_PORT_B_write_enable_reg = DFFE(M1_q_a[4]_PORT_B_write_enable, M1_q_a[4]_clock_1, , , );
M1_q_a[4]_clock_0 = clk;
M1_q_a[4]_clock_1 = A1L5;
M1_q_a[4]_PORT_A_data_out = MEMORY(M1_q_a[4]_PORT_A_data_in_reg, M1_q_a[4]_PORT_B_data_in_reg, M1_q_a[4]_PORT_A_address_reg, M1_q_a[4]_PORT_B_address_reg, M1_q_a[4]_PORT_A_write_enable_reg, M1_q_a[4]_PORT_B_write_enable_reg, , , M1_q_a[4]_clock_0, M1_q_a[4]_clock_1, , , , );
M1_q_a[4]_PORT_A_data_out_reg = DFFE(M1_q_a[4]_PORT_A_data_out, M1_q_a[4]_clock_0, , , );
M1_q_a[4] = M1_q_a[4]_PORT_A_data_out_reg[0];

--M1_q_b[4] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_b[4]
M1_q_b[4]_PORT_A_data_in = VCC;
M1_q_b[4]_PORT_A_data_in_reg = DFFE(M1_q_b[4]_PORT_A_data_in, M1_q_b[4]_clock_0, , , );
M1_q_b[4]_PORT_B_data_in = N1_ram_rom_data_reg[4];
M1_q_b[4]_PORT_B_data_in_reg = DFFE(M1_q_b[4]_PORT_B_data_in, M1_q_b[4]_clock_1, , , );
M1_q_b[4]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_b[4]_PORT_A_address_reg = DFFE(M1_q_b[4]_PORT_A_address, M1_q_b[4]_clock_0, , , );
M1_q_b[4]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_b[4]_PORT_B_address_reg = DFFE(M1_q_b[4]_PORT_B_address, M1_q_b[4]_clock_1, , , );
M1_q_b[4]_PORT_A_write_enable = GND;
M1_q_b[4]_PORT_A_write_enable_reg = DFFE(M1_q_b[4]_PORT_A_write_enable, M1_q_b[4]_clock_0, , , );
M1_q_b[4]_PORT_B_write_enable = N1L3;
M1_q_b[4]_PORT_B_write_enable_reg = DFFE(M1_q_b[4]_PORT_B_write_enable, M1_q_b[4]_clock_1, , , );
M1_q_b[4]_clock_0 = clk;
M1_q_b[4]_clock_1 = A1L5;
M1_q_b[4]_PORT_B_data_out = MEMORY(M1_q_b[4]_PORT_A_data_in_reg, M1_q_b[4]_PORT_B_data_in_reg, M1_q_b[4]_PORT_A_address_reg, M1_q_b[4]_PORT_B_address_reg, M1_q_b[4]_PORT_A_write_enable_reg, M1_q_b[4]_PORT_B_write_enable_reg, , , M1_q_b[4]_clock_0, M1_q_b[4]_clock_1, , , , );
M1_q_b[4] = M1_q_b[4]_PORT_B_data_out[0];


--M1_q_a[5] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_a[5]_PORT_A_data_in = VCC;
M1_q_a[5]_PORT_A_data_in_reg = DFFE(M1_q_a[5]_PORT_A_data_in, M1_q_a[5]_clock_0, , , );
M1_q_a[5]_PORT_B_data_in = N1_ram_rom_data_reg[5];
M1_q_a[5]_PORT_B_data_in_reg = DFFE(M1_q_a[5]_PORT_B_data_in, M1_q_a[5]_clock_1, , , );
M1_q_a[5]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_a[5]_PORT_A_address_reg = DFFE(M1_q_a[5]_PORT_A_address, M1_q_a[5]_clock_0, , , );
M1_q_a[5]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_a[5]_PORT_B_address_reg = DFFE(M1_q_a[5]_PORT_B_address, M1_q_a[5]_clock_1, , , );
M1_q_a[5]_PORT_A_write_enable = GND;
M1_q_a[5]_PORT_A_write_enable_reg = DFFE(M1_q_a[5]_PORT_A_write_enable, M1_q_a[5]_clock_0, , , );
M1_q_a[5]_PORT_B_write_enable = N1L3;
M1_q_a[5]_PORT_B_write_enable_reg = DFFE(M1_q_a[5]_PORT_B_write_enable, M1_q_a[5]_clock_1, , , );
M1_q_a[5]_clock_0 = clk;
M1_q_a[5]_clock_1 = A1L5;
M1_q_a[5]_PORT_A_data_out = MEMORY(M1_q_a[5]_PORT_A_data_in_reg, M1_q_a[5]_PORT_B_data_in_reg, M1_q_a[5]_PORT_A_address_reg, M1_q_a[5]_PORT_B_address_reg, M1_q_a[5]_PORT_A_write_enable_reg, M1_q_a[5]_PORT_B_write_enable_reg, , , M1_q_a[5]_clock_0, M1_q_a[5]_clock_1, , , , );
M1_q_a[5]_PORT_A_data_out_reg = DFFE(M1_q_a[5]_PORT_A_data_out, M1_q_a[5]_clock_0, , , );
M1_q_a[5] = M1_q_a[5]_PORT_A_data_out_reg[0];

--M1_q_b[5] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_b[5]
M1_q_b[5]_PORT_A_data_in = VCC;
M1_q_b[5]_PORT_A_data_in_reg = DFFE(M1_q_b[5]_PORT_A_data_in, M1_q_b[5]_clock_0, , , );
M1_q_b[5]_PORT_B_data_in = N1_ram_rom_data_reg[5];
M1_q_b[5]_PORT_B_data_in_reg = DFFE(M1_q_b[5]_PORT_B_data_in, M1_q_b[5]_clock_1, , , );
M1_q_b[5]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_b[5]_PORT_A_address_reg = DFFE(M1_q_b[5]_PORT_A_address, M1_q_b[5]_clock_0, , , );
M1_q_b[5]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_b[5]_PORT_B_address_reg = DFFE(M1_q_b[5]_PORT_B_address, M1_q_b[5]_clock_1, , , );
M1_q_b[5]_PORT_A_write_enable = GND;
M1_q_b[5]_PORT_A_write_enable_reg = DFFE(M1_q_b[5]_PORT_A_write_enable, M1_q_b[5]_clock_0, , , );
M1_q_b[5]_PORT_B_write_enable = N1L3;
M1_q_b[5]_PORT_B_write_enable_reg = DFFE(M1_q_b[5]_PORT_B_write_enable, M1_q_b[5]_clock_1, , , );
M1_q_b[5]_clock_0 = clk;