sine.fit.eqn

原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成

M1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
M1_q_b[0]_PORT_A_data_in_reg = DFFE(M1_q_b[0]_PORT_A_data_in, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_data_in = BUS(N1_ram_rom_data_reg[0], N1_ram_rom_data_reg[1], N1_ram_rom_data_reg[2], N1_ram_rom_data_reg[3], N1_ram_rom_data_reg[4], N1_ram_rom_data_reg[5], N1_ram_rom_data_reg[6], N1_ram_rom_data_reg[7]);
M1_q_b[0]_PORT_B_data_in_reg = DFFE(M1_q_b[0]_PORT_B_data_in, M1_q_b[0]_clock_1, , , );
M1_q_b[0]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_b[0]_PORT_A_address_reg = DFFE(M1_q_b[0]_PORT_A_address, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_b[0]_PORT_B_address_reg = DFFE(M1_q_b[0]_PORT_B_address, M1_q_b[0]_clock_1, , , );
M1_q_b[0]_PORT_A_write_enable = GND;
M1_q_b[0]_PORT_A_write_enable_reg = DFFE(M1_q_b[0]_PORT_A_write_enable, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_write_enable = N1L3;
M1_q_b[0]_PORT_B_write_enable_reg = DFFE(M1_q_b[0]_PORT_B_write_enable, M1_q_b[0]_clock_1, , , );
M1_q_b[0]_clock_0 = GLOBAL(A1L16);
M1_q_b[0]_clock_1 = GLOBAL(A1L6);
M1_q_b[0]_PORT_B_data_out = MEMORY(M1_q_b[0]_PORT_A_data_in_reg, M1_q_b[0]_PORT_B_data_in_reg, M1_q_b[0]_PORT_A_address_reg, M1_q_b[0]_PORT_B_address_reg, M1_q_b[0]_PORT_A_write_enable_reg, M1_q_b[0]_PORT_B_write_enable_reg, , , M1_q_b[0]_clock_0, M1_q_b[0]_clock_1, , , , );
M1_q_b[5] = M1_q_b[0]_PORT_B_data_out[5];

--M1_q_b[4] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_b[4] at M4K_X52_Y21
M1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
M1_q_b[0]_PORT_A_data_in_reg = DFFE(M1_q_b[0]_PORT_A_data_in, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_data_in = BUS(N1_ram_rom_data_reg[0], N1_ram_rom_data_reg[1], N1_ram_rom_data_reg[2], N1_ram_rom_data_reg[3], N1_ram_rom_data_reg[4], N1_ram_rom_data_reg[5], N1_ram_rom_data_reg[6], N1_ram_rom_data_reg[7]);
M1_q_b[0]_PORT_B_data_in_reg = DFFE(M1_q_b[0]_PORT_B_data_in, M1_q_b[0]_clock_1, , , );
M1_q_b[0]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_b[0]_PORT_A_address_reg = DFFE(M1_q_b[0]_PORT_A_address, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_b[0]_PORT_B_address_reg = DFFE(M1_q_b[0]_PORT_B_address, M1_q_b[0]_clock_1, , , );
M1_q_b[0]_PORT_A_write_enable = GND;
M1_q_b[0]_PORT_A_write_enable_reg = DFFE(M1_q_b[0]_PORT_A_write_enable, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_write_enable = N1L3;
M1_q_b[0]_PORT_B_write_enable_reg = DFFE(M1_q_b[0]_PORT_B_write_enable, M1_q_b[0]_clock_1, , , );
M1_q_b[0]_clock_0 = GLOBAL(A1L16);
M1_q_b[0]_clock_1 = GLOBAL(A1L6);
M1_q_b[0]_PORT_B_data_out = MEMORY(M1_q_b[0]_PORT_A_data_in_reg, M1_q_b[0]_PORT_B_data_in_reg, M1_q_b[0]_PORT_A_address_reg, M1_q_b[0]_PORT_B_address_reg, M1_q_b[0]_PORT_A_write_enable_reg, M1_q_b[0]_PORT_B_write_enable_reg, , , M1_q_b[0]_clock_0, M1_q_b[0]_clock_1, , , , );
M1_q_b[4] = M1_q_b[0]_PORT_B_data_out[4];

--M1_q_b[3] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_b[3] at M4K_X52_Y21
M1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
M1_q_b[0]_PORT_A_data_in_reg = DFFE(M1_q_b[0]_PORT_A_data_in, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_data_in = BUS(N1_ram_rom_data_reg[0], N1_ram_rom_data_reg[1], N1_ram_rom_data_reg[2], N1_ram_rom_data_reg[3], N1_ram_rom_data_reg[4], N1_ram_rom_data_reg[5], N1_ram_rom_data_reg[6], N1_ram_rom_data_reg[7]);
M1_q_b[0]_PORT_B_data_in_reg = DFFE(M1_q_b[0]_PORT_B_data_in, M1_q_b[0]_clock_1, , , );
M1_q_b[0]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_b[0]_PORT_A_address_reg = DFFE(M1_q_b[0]_PORT_A_address, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_b[0]_PORT_B_address_reg = DFFE(M1_q_b[0]_PORT_B_address, M1_q_b[0]_clock_1, , , );
M1_q_b[0]_PORT_A_write_enable = GND;
M1_q_b[0]_PORT_A_write_enable_reg = DFFE(M1_q_b[0]_PORT_A_write_enable, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_write_enable = N1L3;
M1_q_b[0]_PORT_B_write_enable_reg = DFFE(M1_q_b[0]_PORT_B_write_enable, M1_q_b[0]_clock_1, , , );
M1_q_b[0]_clock_0 = GLOBAL(A1L16);
M1_q_b[0]_clock_1 = GLOBAL(A1L6);
M1_q_b[0]_PORT_B_data_out = MEMORY(M1_q_b[0]_PORT_A_data_in_reg, M1_q_b[0]_PORT_B_data_in_reg, M1_q_b[0]_PORT_A_address_reg, M1_q_b[0]_PORT_B_address_reg, M1_q_b[0]_PORT_A_write_enable_reg, M1_q_b[0]_PORT_B_write_enable_reg, , , M1_q_b[0]_clock_0, M1_q_b[0]_clock_1, , , , );
M1_q_b[3] = M1_q_b[0]_PORT_B_data_out[3];

--M1_q_b[2] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_b[2] at M4K_X52_Y21
M1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
M1_q_b[0]_PORT_A_data_in_reg = DFFE(M1_q_b[0]_PORT_A_data_in, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_data_in = BUS(N1_ram_rom_data_reg[0], N1_ram_rom_data_reg[1], N1_ram_rom_data_reg[2], N1_ram_rom_data_reg[3], N1_ram_rom_data_reg[4], N1_ram_rom_data_reg[5], N1_ram_rom_data_reg[6], N1_ram_rom_data_reg[7]);
M1_q_b[0]_PORT_B_data_in_reg = DFFE(M1_q_b[0]_PORT_B_data_in, M1_q_b[0]_clock_1, , , );
M1_q_b[0]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_b[0]_PORT_A_address_reg = DFFE(M1_q_b[0]_PORT_A_address, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_b[0]_PORT_B_address_reg = DFFE(M1_q_b[0]_PORT_B_address, M1_q_b[0]_clock_1, , , );
M1_q_b[0]_PORT_A_write_enable = GND;
M1_q_b[0]_PORT_A_write_enable_reg = DFFE(M1_q_b[0]_PORT_A_write_enable, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_write_enable = N1L3;
M1_q_b[0]_PORT_B_write_enable_reg = DFFE(M1_q_b[0]_PORT_B_write_enable, M1_q_b[0]_clock_1, , , );
M1_q_b[0]_clock_0 = GLOBAL(A1L16);
M1_q_b[0]_clock_1 = GLOBAL(A1L6);
M1_q_b[0]_PORT_B_data_out = MEMORY(M1_q_b[0]_PORT_A_data_in_reg, M1_q_b[0]_PORT_B_data_in_reg, M1_q_b[0]_PORT_A_address_reg, M1_q_b[0]_PORT_B_address_reg, M1_q_b[0]_PORT_A_write_enable_reg, M1_q_b[0]_PORT_B_write_enable_reg, , , M1_q_b[0]_clock_0, M1_q_b[0]_clock_1, , , , );
M1_q_b[2] = M1_q_b[0]_PORT_B_data_out[2];

--M1_q_b[1] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_b[1] at M4K_X52_Y21
M1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
M1_q_b[0]_PORT_A_data_in_reg = DFFE(M1_q_b[0]_PORT_A_data_in, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_data_in = BUS(N1_ram_rom_data_reg[0], N1_ram_rom_data_reg[1], N1_ram_rom_data_reg[2], N1_ram_rom_data_reg[3], N1_ram_rom_data_reg[4], N1_ram_rom_data_reg[5], N1_ram_rom_data_reg[6], N1_ram_rom_data_reg[7]);
M1_q_b[0]_PORT_B_data_in_reg = DFFE(M1_q_b[0]_PORT_B_data_in, M1_q_b[0]_clock_1, , , );
M1_q_b[0]_PORT_A_address = BUS(q1[0], q1[1], q1[2], q1[3], q1[4], q1[5]);
M1_q_b[0]_PORT_A_address_reg = DFFE(M1_q_b[0]_PORT_A_address, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_address = BUS(N1_ram_rom_addr_reg[0], N1_ram_rom_addr_reg[1], N1_ram_rom_addr_reg[2], N1_ram_rom_addr_reg[3], N1_ram_rom_addr_reg[4], N1_ram_rom_addr_reg[5]);
M1_q_b[0]_PORT_B_address_reg = DFFE(M1_q_b[0]_PORT_B_address, M1_q_b[0]_clock_1, , , );
M1_q_b[0]_PORT_A_write_enable = GND;
M1_q_b[0]_PORT_A_write_enable_reg = DFFE(M1_q_b[0]_PORT_A_write_enable, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_write_enable = N1L3;
M1_q_b[0]_PORT_B_write_enable_reg = DFFE(M1_q_b[0]_PORT_B_write_enable, M1_q_b[0]_clock_1, , , );
M1_q_b[0]_clock_0 = GLOBAL(A1L16);
M1_q_b[0]_clock_1 = GLOBAL(A1L6);
M1_q_b[0]_PORT_B_data_out = MEMORY(M1_q_b[0]_PORT_A_data_in_reg, M1_q_b[0]_PORT_B_data_in_reg, M1_q_b[0]_PORT_A_address_reg, M1_q_b[0]_PORT_B_address_reg, M1_q_b[0]_PORT_A_write_enable_reg, M1_q_b[0]_PORT_B_write_enable_reg, , , M1_q_b[0]_clock_0, M1_q_b[0]_clock_1, , , , );
M1_q_b[1] = M1_q_b[0]_PORT_B_data_out[1];


--A1L7 is altera_internal_jtag~TDO at JTAG_X1_Y19_N0
A1L7 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , B1L19);

--A1L8 is altera_internal_jtag~TMSUTAP at JTAG_X1_Y19_N0
A1L8 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , B1L19);

--A1L5 is altera_internal_jtag~TCKUTAP at JTAG_X1_Y19_N0
A1L5 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , B1L19);

--altera_internal_jtag is altera_internal_jtag at JTAG_X1_Y19_N0
altera_internal_jtag = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , B1L19);


--H1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5] at LCFF_X45_Y21_N13
H1_state[5] = AMPP_FUNCTION(A1L6, H1L23);


--D4_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] at LCFF_X47_Y21_N23
D4_Q[2] = AMPP_FUNCTION(A1L6, B1L22, B1L3, B1L28);


--B1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode at LCFF_X46_Y21_N31
B1_jtag_debug_mode = AMPP_FUNCTION(A1L6, B1L39, H1L3);


--D6_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] at LCFF_X45_Y21_N29
D6_Q[0] = AMPP_FUNCTION(A1L6, altera_internal_jtag, B1L3, GND, B1L25);


--B1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1 at LCFF_X46_Y21_N5
B1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L6, A1L45, H1L3, H1_state[12]);


--D2_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] at LCFF_X45_Y21_N3
D2_Q[0] = AMPP_FUNCTION(A1L6, D2L4, B1L3);


--N1L14 is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|name_gen~33 at LCCOMB_X45_Y21_N28
N1L14 = AMPP_FUNCTION(B1_jtag_debug_mode_usr1, B1_jtag_debug_mode, D6_Q[0], D2_Q[0]);


--N1L3 is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|enable_write~11 at LCCOMB_X46_Y21_N6
N1L3 = AMPP_FUNCTION(D4_Q[2], N1L14, H1_state[5]);


--q1[0] is q1[0] at LCFF_X51_Y21_N9
q1[0] = DFFEAS(A1L28, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--q1[1] is q1[1] at LCFF_X51_Y21_N11
q1[1] = DFFEAS(A1L31, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--q1[2] is q1[2] at LCFF_X51_Y21_N13
q1[2] = DFFEAS(A1L34, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--q1[3] is q1[3] at LCFF_X51_Y21_N15
q1[3] = DFFEAS(A1L37, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--q1[4] is q1[4] at LCFF_X51_Y21_N17
q1[4] = DFFEAS(A1L40, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--q1[5] is q1[5] at LCFF_X51_Y21_N19
q1[5] = DFFEAS(A1L43, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--N1_ram_rom_data_reg[0] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] at LCFF_X48_Y21_N9
N1_ram_rom_data_reg[0] = AMPP_FUNCTION(A1L6, N1L50, N1L49);


--N1_ram_rom_addr_reg[0] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0] at LCFF_X46_Y21_N11
N1_ram_rom_addr_reg[0] = AMPP_FUNCTION(A1L6, N1L23, N1_ram_rom_addr_reg[1], !D4L3, N1L15);


--N1_ram_rom_addr_reg[1] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1] at LCFF_X46_Y21_N13
N1_ram_rom_addr_reg[1] = AMPP_FUNCTION(A1L6, N1L26, N1_ram_rom_addr_reg[2], !D4L3, N1L15);


--N1_ram_rom_addr_reg[2] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2] at LCFF_X46_Y21_N15
N1_ram_rom_addr_reg[2] = AMPP_FUNCTION(A1L6, N1L29, N1_ram_rom_addr_reg[3], !D4L3, N1L15);


--N1_ram_rom_addr_reg[3] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3] at LCFF_X46_Y21_N17
N1_ram_rom_addr_reg[3] = AMPP_FUNCTION(A1L6, N1L32, N1_ram_rom_addr_reg[4], !D4L3, N1L15);


--N1_ram_rom_addr_reg[4] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4] at LCFF_X46_Y21_N19
N1_ram_rom_addr_reg[4] = AMPP_FUNCTION(A1L6, N1L35, N1_ram_rom_addr_reg[5], !D4L3, N1L15);


--N1_ram_rom_addr_reg[5] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5] at LCFF_X46_Y21_N21
N1_ram_rom_addr_reg[5] = AMPP_FUNCTION(A1L6, N1L38, altera_internal_jtag, !D4L3, N1L15);


--N1_ram_rom_data_reg[1] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1] at LCFF_X48_Y21_N11
N1_ram_rom_data_reg[1] = AMPP_FUNCTION(A1L6, N1L51, N1L49);


--N1_ram_rom_data_reg[2] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2] at LCFF_X48_Y21_N19
N1_ram_rom_data_reg[2] = AMPP_FUNCTION(A1L6, N1L52, N1L49);


--N1_ram_rom_data_reg[3] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3] at LCFF_X48_Y21_N25
N1_ram_rom_data_reg[3] = AMPP_FUNCTION(A1L6, N1L53, N1L49);


--N1_ram_rom_data_reg[4] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4] at LCFF_X48_Y21_N3
N1_ram_rom_data_reg[4] = AMPP_FUNCTION(A1L6, N1L54, N1L49);


--N1_ram_rom_data_reg[5] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5] at LCFF_X48_Y21_N7
N1_ram_rom_data_reg[5] = AMPP_FUNCTION(A1L6, N1L55, N1L49);


--N1_ram_rom_data_reg[6] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6] at LCFF_X48_Y21_N23
N1_ram_rom_data_reg[6] = AMPP_FUNCTION(A1L6, N1L56, N1L49);


--N1_ram_rom_data_reg[7] is rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7] at LCFF_X48_Y21_N27
N1_ram_rom_data_reg[7] = AMPP_FUNCTION(A1L6, N1L57, N1L49);


--B1_hub_tdo is sld_hub:sld_hub_inst|hub_tdo at LCFF_X47_Y21_N1
B1_hub_tdo = AMPP_FUNCTION(!A1L6, B1L17, !H1_state[8]);


--H1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] at LCFF_X45_Y21_N1
H1_state[3] = AMPP_FUNCTION(A1L6, H1L20);


--H1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] at LCFF_X42_Y20_N25