div_clock.vhd

来自「原创：基于VHDL语言编写的电子钟。采用模块化编写」· VHDL 代码 · 共 40 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity div_clock is
port(
	clk:in std_logic;				--系统时钟，选定5MHZ
	clk_1hz:out std_logic;			--用于时间显示，为1hz
	clk_100hz:out std_logic		--用于动态扫描显示 扫描间隔为10ms
);
end entity div_clock;

architecture beh of div_clock is
signal count1:integer range 0 to 5000;
signal count2:integer range 0 to 10;
signal count3:integer range 0 to 50;
signal clk_1,clk_100:std_logic;
begin
	process(clk)
	begin
	if(clk'event and clk='1')then
	count1<=count1+1;
	if(count1=5000)then
		count1<=0;
		count2<=count2+1;
		if(count2=5)then
			count2<=0;
			clk_100<=not clk_100;		--产生100hz时钟
			count3<=count3+1;
			if(count3=50)then
				count3<=0;
				clk_1<=not clk_1;			--产生1hz时钟
				end if;
		    end if;
		end if;
	end if;
	end process;
	clk_1hz<=clk_1;
	clk_100hz<=clk_100;
end architecture beh;