clock.hier_info

原创：基于VHDL语言编写的电子钟。采用模块化编写

|clock
dp <= disp:inst2.dp
CLK => div_clock:inst6.clk
RESET => disp:inst2.rst
RESET => sel_mode:inst9.rst
RESET => counter60:inst.clr
RESET => counter60:inst3.clr
RESET => counter24:inst4.clr
KEY_CHANGE => sel_mode:inst9.key_clk
KEY_MODE => sel_mode:inst9.key_mode
disp[0] <= bcd_decoder:inst5.LED7S[0]
disp[1] <= bcd_decoder:inst5.LED7S[1]
disp[2] <= bcd_decoder:inst5.LED7S[2]
disp[3] <= bcd_decoder:inst5.LED7S[3]
disp[4] <= bcd_decoder:inst5.LED7S[4]
disp[5] <= bcd_decoder:inst5.LED7S[5]
disp[6] <= bcd_decoder:inst5.LED7S[6]
sel[0] <= disp:inst2.sel[0]
sel[1] <= disp:inst2.sel[1]
sel[2] <= disp:inst2.sel[2]
sel[3] <= disp:inst2.sel[3]
sel[4] <= disp:inst2.sel[4]
sel[5] <= disp:inst2.sel[5]


|clock|disp:inst2
clk1 => count[1].CLK
clk1 => count[0].CLK
clk1 => disp[3]~reg0.CLK
clk1 => disp[2]~reg0.CLK
clk1 => disp[1]~reg0.CLK
clk1 => disp[0]~reg0.CLK
clk1 => dp~reg0.CLK
clk1 => sel[5]~reg0.CLK
clk1 => sel[4]~reg0.CLK
clk1 => sel[3]~reg0.CLK
clk1 => sel[2]~reg0.CLK
clk1 => sel[1]~reg0.CLK
clk1 => sel[0]~reg0.CLK
clk1 => count[2].CLK
rst => disp[2]~reg0.ACLR
rst => disp[1]~reg0.ACLR
rst => disp[0]~reg0.ACLR
rst => dp~reg0.ACLR
rst => sel[5]~reg0.ACLR
rst => sel[4]~reg0.ACLR
rst => sel[3]~reg0.ACLR
rst => sel[2]~reg0.ACLR
rst => sel[1]~reg0.ACLR
rst => sel[0]~reg0.ACLR
rst => count[1].ACLR
rst => disp[3]~reg0.ACLR
rst => count[0].ACLR
rst => count[2].ACLR
secl[0] => Mux~3.IN2
secl[1] => Mux~2.IN2
secl[2] => Mux~1.IN2
secl[3] => Mux~0.IN2
sech[0] => Mux~3.IN3
sech[1] => Mux~2.IN3
sech[2] => Mux~1.IN3
sech[3] => Mux~0.IN3
minl[0] => Mux~3.IN4
minl[1] => Mux~2.IN4
minl[2] => Mux~1.IN4
minl[3] => Mux~0.IN4
minh[0] => Mux~3.IN5
minh[1] => Mux~2.IN5
minh[2] => Mux~1.IN5
minh[3] => Mux~0.IN5
hourl[0] => Mux~3.IN6
hourl[1] => Mux~2.IN6
hourl[2] => Mux~1.IN6
hourl[3] => Mux~0.IN6
hourh[0] => Mux~3.IN7
hourh[1] => Mux~2.IN7
hourh[2] => Mux~1.IN7
hourh[3] => Mux~0.IN7
disp[0] <= disp[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[1] <= disp[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[2] <= disp[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[3] <= disp[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dp <= dp~reg0.DB_MAX_OUTPUT_PORT_TYPE
sel[0] <= sel[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sel[1] <= sel[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sel[2] <= sel[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sel[3] <= sel[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sel[4] <= sel[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sel[5] <= sel[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|clock|div_clock:inst6
clk => count1[11].CLK
clk => count1[10].CLK
clk => count1[9].CLK
clk => count1[8].CLK
clk => count1[7].CLK
clk => count1[6].CLK
clk => count1[5].CLK
clk => count1[4].CLK
clk => count1[3].CLK
clk => count1[2].CLK
clk => count1[1].CLK
clk => count1[0].CLK
clk => count2[3].CLK
clk => count2[2].CLK
clk => count2[1].CLK
clk => count2[0].CLK
clk => clk_100.CLK
clk => count3[5].CLK
clk => count3[4].CLK
clk => count3[3].CLK
clk => count3[2].CLK
clk => count3[1].CLK
clk => count3[0].CLK
clk => clk_1.CLK
clk => count1[12].CLK
clk_1hz <= clk_1.DB_MAX_OUTPUT_PORT_TYPE
clk_100hz <= clk_100.DB_MAX_OUTPUT_PORT_TYPE


|clock|counter24:inst4
clk => l[2].CLK
clk => l[1].CLK
clk => l[0].CLK
clk => h[1].CLK
clk => h[0].CLK
clk => cout~reg0.CLK
clk => l[3].CLK
clr => l[2].ACLR
clr => l[1].ACLR
clr => l[0].ACLR
clr => h[1].ACLR
clr => h[0].ACLR
clr => cout~reg0.ACLR
clr => l[3].ACLR
cout <= cout~reg0.DB_MAX_OUTPUT_PORT_TYPE
low[0] <= l[0].DB_MAX_OUTPUT_PORT_TYPE
low[1] <= l[1].DB_MAX_OUTPUT_PORT_TYPE
low[2] <= l[2].DB_MAX_OUTPUT_PORT_TYPE
low[3] <= l[3].DB_MAX_OUTPUT_PORT_TYPE
high[0] <= h[0].DB_MAX_OUTPUT_PORT_TYPE
high[1] <= h[1].DB_MAX_OUTPUT_PORT_TYPE
high[2] <= <GND>
high[3] <= <GND>


|clock|counter60:inst3
clk => l[2].CLK
clk => l[1].CLK
clk => l[0].CLK
clk => h[2].CLK
clk => h[1].CLK
clk => h[0].CLK
clk => cout~reg0.CLK
clk => l[3].CLK
clr => l[2].ACLR
clr => l[1].ACLR
clr => l[0].ACLR
clr => h[2].ACLR
clr => h[1].ACLR
clr => h[0].ACLR
clr => cout~reg0.ACLR
clr => l[3].ACLR
cout <= cout~reg0.DB_MAX_OUTPUT_PORT_TYPE
low[0] <= l[0].DB_MAX_OUTPUT_PORT_TYPE
low[1] <= l[1].DB_MAX_OUTPUT_PORT_TYPE
low[2] <= l[2].DB_MAX_OUTPUT_PORT_TYPE
low[3] <= l[3].DB_MAX_OUTPUT_PORT_TYPE
high[0] <= h[0].DB_MAX_OUTPUT_PORT_TYPE
high[1] <= h[1].DB_MAX_OUTPUT_PORT_TYPE
high[2] <= h[2].DB_MAX_OUTPUT_PORT_TYPE
high[3] <= <GND>


|clock|sel_mode:inst9
rst => mode[0].ACLR
rst => mode[1].ACLR
clk => Mux~0.IN3
key_clk => Mux~1.IN3
key_clk => Mux~2.IN3
key_clk => Mux~3.IN3
key_mode => mode[0].CLK
key_mode => mode[1].CLK
qclk <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE
sel_sec <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
sel_min <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
sel_hour <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE


|clock|counter60:inst
clk => l[2].CLK
clk => l[1].CLK
clk => l[0].CLK
clk => h[2].CLK
clk => h[1].CLK
clk => h[0].CLK
clk => cout~reg0.CLK
clk => l[3].CLK
clr => l[2].ACLR
clr => l[1].ACLR
clr => l[0].ACLR
clr => h[2].ACLR
clr => h[1].ACLR
clr => h[0].ACLR
clr => cout~reg0.ACLR
clr => l[3].ACLR
cout <= cout~reg0.DB_MAX_OUTPUT_PORT_TYPE
low[0] <= l[0].DB_MAX_OUTPUT_PORT_TYPE
low[1] <= l[1].DB_MAX_OUTPUT_PORT_TYPE
low[2] <= l[2].DB_MAX_OUTPUT_PORT_TYPE
low[3] <= l[3].DB_MAX_OUTPUT_PORT_TYPE
high[0] <= h[0].DB_MAX_OUTPUT_PORT_TYPE
high[1] <= h[1].DB_MAX_OUTPUT_PORT_TYPE
high[2] <= h[2].DB_MAX_OUTPUT_PORT_TYPE
high[3] <= <GND>


|clock|bcd_decoder:inst5
ina[0] => Mux~0.IN19
ina[0] => Mux~1.IN19
ina[0] => Mux~2.IN19
ina[0] => Mux~3.IN19
ina[0] => Mux~4.IN19
ina[0] => Mux~5.IN19
ina[0] => Mux~6.IN19
ina[1] => Mux~0.IN18
ina[1] => Mux~1.IN18
ina[1] => Mux~2.IN18
ina[1] => Mux~3.IN18
ina[1] => Mux~4.IN18
ina[1] => Mux~5.IN18
ina[1] => Mux~6.IN18
ina[2] => Mux~0.IN17
ina[2] => Mux~1.IN17
ina[2] => Mux~2.IN17
ina[2] => Mux~3.IN17
ina[2] => Mux~4.IN17
ina[2] => Mux~5.IN17
ina[2] => Mux~6.IN17
ina[3] => Mux~0.IN16
ina[3] => Mux~1.IN16
ina[3] => Mux~2.IN16
ina[3] => Mux~3.IN16
ina[3] => Mux~4.IN16
ina[3] => Mux~5.IN16
ina[3] => Mux~6.IN16
LED7S[0] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
LED7S[1] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
LED7S[2] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
LED7S[3] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
LED7S[4] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
LED7S[5] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
LED7S[6] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE