clock.map.qmsg

原创：基于VHDL语言编写的电子钟。采用模块化编写

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 11 22:54:30 2008 " "Info: Processing started: Tue Nov 11 22:54:30 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file clock.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter60.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter60.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter60-behave " "Info: Found design unit 1: counter60-behave" {  } { { "counter60.vhd" "" { Text "D:/quartus/myproject/clock/counter60.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter60 " "Info: Found entity 1: counter60" {  } { { "counter60.vhd" "" { Text "D:/quartus/myproject/clock/counter60.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter24.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter24.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter24-beh " "Info: Found design unit 1: counter24-beh" {  } { { "counter24.vhd" "" { Text "D:/quartus/myproject/clock/counter24.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter24 " "Info: Found entity 1: counter24" {  } { { "counter24.vhd" "" { Text "D:/quartus/myproject/clock/counter24.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bcd_decoder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file bcd_decoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bcd_decoder-one " "Info: Found design unit 1: bcd_decoder-one" {  } { { "bcd_decoder.vhd" "" { Text "D:/quartus/myproject/clock/bcd_decoder.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 bcd_decoder " "Info: Found entity 1: bcd_decoder" {  } { { "bcd_decoder.vhd" "" { Text "D:/quartus/myproject/clock/bcd_decoder.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sel_mode.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sel_mode.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sel_mode-beh " "Info: Found design unit 1: sel_mode-beh" {  } { { "sel_mode.vhd" "" { Text "D:/quartus/myproject/clock/sel_mode.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sel_mode " "Info: Found entity 1: sel_mode" {  } { { "sel_mode.vhd" "" { Text "D:/quartus/myproject/clock/sel_mode.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "disp.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file disp.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 disp-beh " "Info: Found design unit 1: disp-beh" {  } { { "disp.vhd" "" { Text "D:/quartus/myproject/clock/disp.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 disp " "Info: Found entity 1: disp" {  } { { "disp.vhd" "" { Text "D:/quartus/myproject/clock/disp.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div_clock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div_clock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div_clock-beh " "Info: Found design unit 1: div_clock-beh" {  } { { "div_clock.vhd" "" { Text "D:/quartus/myproject/clock/div_clock.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 div_clock " "Info: Found entity 1: div_clock" {  } { { "div_clock.vhd" "" { Text "D:/quartus/myproject/clock/div_clock.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Info: Elaborating entity \"clock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "disp disp:inst2 " "Info: Elaborating entity \"disp\" for hierarchy \"disp:inst2\"" {  } { { "clock.bdf" "inst2" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { -32 768 920 160 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div_clock div_clock:inst6 " "Info: Elaborating entity \"div_clock\" for hierarchy \"div_clock:inst6\"" {  } { { "clock.bdf" "inst6" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { -152 280 400 -56 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter24 counter24:inst4 " "Info: Elaborating entity \"counter24\" for hierarchy \"counter24:inst4\"" {  } { { "clock.bdf" "inst4" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 224 584 696 320 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter60 counter60:inst3 " "Info: Elaborating entity \"counter60\" for hierarchy \"counter60:inst3\"" {  } { { "clock.bdf" "inst3" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 96 584 696 192 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sel_mode sel_mode:inst9 " "Info: Elaborating entity \"sel_mode\" for hierarchy \"sel_mode:inst9\"" {  } { { "clock.bdf" "inst9" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { -8 288 432 120 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "sel_mode.vhd(32) " "Info (10425): VHDL Case Statement information at sel_mode.vhd(32): OTHERS choice is never selected" {  } { { "sel_mode.vhd" "" { Text "D:/quartus/myproject/clock/sel_mode.vhd" 32 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bcd_decoder bcd_decoder:inst5 " "Info: Elaborating entity \"bcd_decoder\" for hierarchy \"bcd_decoder:inst5\"" {  } { { "clock.bdf" "inst5" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 192 816 968 288 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "bcd_decoder.vhd(32) " "Info (10425): VHDL Case Statement information at bcd_decoder.vhd(32): OTHERS choice is never selected" {  } { { "bcd_decoder.vhd" "" { Text "D:/quartus/myproject/clock/bcd_decoder.vhd" 32 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "153 " "Info: Implemented 153 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "14 " "Info: Implemented 14 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "135 " "Info: Implemented 135 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 11 22:54:48 2008 " "Info: Processing ended: Tue Nov 11 22:54:48 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:21 " "Info: Elapsed time: 00:00:21" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}