counter60.vhd

来自「原创：基于VHDL语言编写的电子钟。采用模块化编写」· VHDL 代码 · 共 56 行

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
use ieee.std_logic_arith.all; 
 
entity counter60 is 
port( 
	clk,clr:in std_logic; 
	cout:out std_logic;
	low,high:out std_logic_vector(3 downto 0));
	 
end counter60; 
 
architecture behave of counter60 is 
 
signal l:integer range 0 to 9; 
signal h:integer range 0 to 5; 
 
begin 
 
	process(clk,clr,l,h) 
	begin 
		if(clr='0')then 
			l<=0; 
			h<=0; 
			cout<='0';
		elsif(clk'event and clk='1')then 
			if(h=5)then 
				if(l>=0 and l<9)then 
					l<=l+1; 
				elsif(l=9)then 
					l<=0; 
					h<=0; 
					cout<='1';
				end if; 
			elsif(h>=0 and h<5)then 
				if(l>=0 and l<9)then 
					l<=l+1; 
					cout<='0';
				elsif(l=9)then 
					l<=0; 
					h<=h+1; 
				end if; 
			else 
				l<=0; 
				h<=0; 
			end if; 
		end if; 
	end process; 
 
	low<=conv_std_logic_vector(l,4); --类型转换函数，把整数转换成标准位矢量
	high<=conv_std_logic_vector(h,4); 
 
end behave;