bcd_decoder.vhd

原创：基于VHDL语言编写的电子钟。采用模块化编写

library ieee;
use ieee.std_logic_1164.all;

entity bcd_decoder is
port(
	ina:in std_logic_vector(3 downto 0);
	LED7S:out std_logic_vector(6 downto 0)
);
end entity bcd_decoder;

ARCHITECTURE one OF bcd_decoder IS
 BEGIN
  PROCESS( ina )
  BEGIN
  CASE  ina  IS
   WHEN "0000" =>  LED7S <= "0111111" ; 
   WHEN "0001" =>  LED7S <= "0000110" ; 
   WHEN "0010" =>  LED7S <= "1011011" ; 
   WHEN "0011" =>  LED7S <= "1001111" ; 
   WHEN "0100" =>  LED7S <= "1100110" ; 
   WHEN "0101" =>  LED7S <= "1101101" ; 
   WHEN "0110" =>  LED7S <= "1111101" ;
   WHEN "0111" =>  LED7S <= "0000111" ;
   WHEN "1000" =>  LED7S <= "1111111" ; 
   WHEN "1001" =>  LED7S <= "1101111" ; 
   WHEN "1010" =>  LED7S <= "1110111" ; 
   WHEN "1011" =>  LED7S <= "1111100" ;
   WHEN "1100" =>  LED7S <= "0111001" ;
   WHEN "1101" =>  LED7S <= "1011110" ; 
   WHEN "1110" =>  LED7S <= "1111001" ;
   WHEN "1111" =>  LED7S <= "1110001" ;
   WHEN OTHERS =>  NULL ;
   END CASE ;
  END PROCESS ;
 END ;