electronic-design-automation.txt

用vhdl语句描述4位等值比较器

4位等值比较器描述方式1
   LIBRARY IEEE;
   USE IEEE.STD_LOGIC_1164.ALL;
ENTITY eqcomp4 IS
      PORT(a,b:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
           equals:OUT STD_LOGIC);
    END eqcomp4;
    ARCHITECTURE behave OF eqcomp4 IS
    BEGIN
    comp:PROCESS(a,b)
    BEGIN
      equals<=‘0’;
      IF a=b THEN
        equals<=‘1’;
      END IF;
   END PROCESS comp;
   END behave;    



4选1多路选择器描述方式1
    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    ENTITY mux4 IS
      PORT(a,b,c,d:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            s:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
            X:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
    END mux4;
    ARCHITECTURE behave OF mux4 IS
    BEGIN
    Mux4:PROCESS(a,b,c,d)
    BEGIN
      IF s=“00” THEN
        X<=a;
      ELSIF s=“01” THEN
        X<=b;
      …
      END IF;
   END PROCESS Mux4;
   END behave;    




4选1多路选择器描述方式2
    ENTITY test_case IS
      PORT(s1,s2:IN STD_LOGIC;
           a,b,c,d:IN STD_LOGIC;
            z:OUT STD_LOGIC);
    END test_case;
   ARCHITECTURE behave OF test_case IS
      SIGNAL s:STD_LOGIC_VECTOR(1 DOWNTO 0);
    BEGIN
      s<=s1&s2;
      PROCESS(s1,s2,a,b,c,d)
      BEGIN
      CASE s IS
        WHEN “00”=>z<=a;
        WHEN “01”=>Z<=b;
        …
        WHEN OTHERS =>Z<=‘X’;
      END CASE;
      END PROCESS;
   END behave;    

8位奇偶校验电路
    LIBRARY IEEE;
     USE IEEE.STD_LOGIC_1164.ALL;
     ENTITY p_check IS
       PORT(a:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
            y:OUT STD_LOGIC);
     END p_check;
     ARCHITECTURE behave OF p_check IS
      SIGNAL tmp:STD_LOGIC;
      BEGIN
      PROCESS(a)
      BEGIN
        tmp<=‘0’;
        FOR n IN 0 TO 7 LOOP
          tmp<=tmp XOR a(n);
        END LOOP;
        y<=tmp;
      END PROCESS;
    END behave;


以WHILE循环编写的8位奇偶校验电路
     LIBRARY IEEE;
     USE IEEE.STD_LOGIC_1164.ALL;
     ENTITY p_check2 IS
       PORT(a:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
            y:OUT STD_LOGIC);
     END p_check2；
 ARCHITECTURE behave OF p_check2 IS
      SIGNAL tmp:STD_LOGIC;
      BEGIN
      PROCESS(a)
      VARIABLE i:INTEGER :=0;
      BEGIN
        tmp<=‘0’;
        WHILE i<8 LOOP
          tmp<=tmp XOR a(i)；
          i:=i+1;
        END LOOP;
        y<=tmp;
      END PROCESS;
    END behave;