scfifo_k7v.tdf

用VERILOG写的FIFO程序

--scfifo ADD_RAM_OUTPUT_REGISTER="OFF" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=256 LPM_SHOWAHEAD="OFF" lpm_width=8 lpm_widthu=8 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" clock data empty full q rdreq wrreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO"
--VERSION_BEGIN 6.0 cbx_altdpram 2006:01:09:10:52:42:SJ cbx_altsyncram 2006:03:30:14:59:04:SJ cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_fifo_common 2006:01:09:11:23:34:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_compare 2006:01:09:11:15:40:SJ cbx_lpm_counter 2006:03:23:14:19:24:SJ cbx_lpm_decode 2006:01:09:11:16:44:SJ cbx_lpm_mux 2006:01:09:11:16:16:SJ cbx_mgl 2006:05:17:10:06:16:SJ cbx_scfifo 2006:01:09:11:24:10:SJ cbx_stratix 2006:05:17:09:28:32:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


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FUNCTION a_dpfifo_rdv (clock, data[7..0], rreq, sclr, wreq)
RETURNS ( empty, full, q[7..0]);

--synthesis_resources = lut 18 M4K 1 
SUBDESIGN scfifo_k7v
( 
	clock	:	input;
	data[7..0]	:	input;
	empty	:	output;
	full	:	output;
	q[7..0]	:	output;
	rdreq	:	input;
	wrreq	:	input;
) 
VARIABLE 
	dpfifo : a_dpfifo_rdv;
	sclr	: NODE;

BEGIN 
	dpfifo.clock = clock;
	dpfifo.data[] = data[];
	dpfifo.rreq = rdreq;
	dpfifo.sclr = sclr;
	dpfifo.wreq = wrreq;
	empty = dpfifo.empty;
	full = dpfifo.full;
	q[] = dpfifo.q[];
	sclr = GND;
END;
--VALID FILE