a_fefifo_18e.tdf

用VERILOG写的FIFO程序

--a_fefifo ALLOW_RWCYCLE_WHEN_FULL="OFF" LPM_NUMWORDS=256 lpm_widthad=8 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" aclr clock empty full rreq sclr wreq
--VERSION_BEGIN 6.0 cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_fifo_common 2006:01:09:11:23:34:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_compare 2006:01:09:11:15:40:SJ cbx_lpm_counter 2006:03:23:14:19:24:SJ cbx_lpm_decode 2006:01:09:11:16:44:SJ cbx_mgl 2006:05:17:10:06:16:SJ cbx_stratix 2006:05:17:09:28:32:SJ cbx_stratixii 2006:03:03:09:35:36:SJ  VERSION_END


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FUNCTION cntr_bc7 (aclr, clock, cnt_en, sclr, updown)
RETURNS ( q[7..0]);

--synthesis_resources = lut 10 
SUBDESIGN a_fefifo_18e
( 
	aclr	:	input;
	clock	:	input;
	empty	:	output;
	full	:	output;
	rreq	:	input;
	sclr	:	input;
	wreq	:	input;
) 
VARIABLE 
	b_full : dffe;
	b_non_empty : dffe;
	count_usedw : cntr_bc7;
	equal_af1[7..0]	: WIRE;
	equal_one[7..0]	: WIRE;
	is_almost_empty0	: WIRE;
	is_almost_empty1	: WIRE;
	is_almost_empty2	: WIRE;
	is_almost_empty3	: WIRE;
	is_almost_empty4	: WIRE;
	is_almost_empty5	: WIRE;
	is_almost_empty6	: WIRE;
	is_almost_empty7	: WIRE;
	is_almost_full0	: WIRE;
	is_almost_full1	: WIRE;
	is_almost_full2	: WIRE;
	is_almost_full3	: WIRE;
	is_almost_full4	: WIRE;
	is_almost_full5	: WIRE;
	is_almost_full6	: WIRE;
	is_almost_full7	: WIRE;
	usedw[7..0]	: WIRE;
	valid_rreq	: WIRE;
	valid_wreq	: WIRE;

BEGIN 
	b_full.CLK = clock;
	b_full.CLRN = (! aclr);
	b_full.D = ((b_full.Q & (b_full.Q $ (sclr # rreq))) # (((! b_full.Q) & b_non_empty.Q) & ((! sclr) & ((is_almost_full7 & wreq) & (! rreq)))));
	b_non_empty.CLK = clock;
	b_non_empty.CLRN = (! aclr);
	b_non_empty.D = (((b_full.Q & (b_full.Q $ sclr)) # (((! b_non_empty.Q) & wreq) & (! sclr))) # (((! b_full.Q) & b_non_empty.Q) & (((! b_full.Q) & b_non_empty.Q) $ (sclr # ((is_almost_empty7 & rreq) & (! wreq))))));
	count_usedw.aclr = aclr;
	count_usedw.clock = clock;
	count_usedw.cnt_en = (valid_wreq $ valid_rreq);
	count_usedw.sclr = sclr;
	count_usedw.updown = valid_wreq;
	empty = (! b_non_empty.Q);
	equal_af1[] = ( B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0");
	equal_one[] = ( B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"0");
	full = b_full.Q;
	is_almost_empty0 = (usedw[0..0] $ equal_one[0..0]);
	is_almost_empty1 = ((usedw[1..1] $ equal_one[1..1]) & is_almost_empty0);
	is_almost_empty2 = ((usedw[2..2] $ equal_one[2..2]) & is_almost_empty1);
	is_almost_empty3 = ((usedw[3..3] $ equal_one[3..3]) & is_almost_empty2);
	is_almost_empty4 = ((usedw[4..4] $ equal_one[4..4]) & is_almost_empty3);
	is_almost_empty5 = ((usedw[5..5] $ equal_one[5..5]) & is_almost_empty4);
	is_almost_empty6 = ((usedw[6..6] $ equal_one[6..6]) & is_almost_empty5);
	is_almost_empty7 = ((usedw[7..7] $ equal_one[7..7]) & is_almost_empty6);
	is_almost_full0 = (usedw[0..0] $ equal_af1[0..0]);
	is_almost_full1 = ((usedw[1..1] $ equal_af1[1..1]) & is_almost_full0);
	is_almost_full2 = ((usedw[2..2] $ equal_af1[2..2]) & is_almost_full1);
	is_almost_full3 = ((usedw[3..3] $ equal_af1[3..3]) & is_almost_full2);
	is_almost_full4 = ((usedw[4..4] $ equal_af1[4..4]) & is_almost_full3);
	is_almost_full5 = ((usedw[5..5] $ equal_af1[5..5]) & is_almost_full4);
	is_almost_full6 = ((usedw[6..6] $ equal_af1[6..6]) & is_almost_full5);
	is_almost_full7 = ((usedw[7..7] $ equal_af1[7..7]) & is_almost_full6);
	usedw[] = count_usedw.q[];
	valid_rreq = (rreq & b_non_empty.Q);
	valid_wreq = (wreq & (! b_full.Q));
END;
--VALID FILE