fifo.tan.qmsg

用VERILOG写的FIFO程序

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "fifo_pll:M3\|altpll:altpll_component\|_clk0 register fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|alt_synch_pipe_oc8:dffpipe_ws_dgrp\|dffpipe_id9:dffpipe10\|dffe11a\[4\] register fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|alt_synch_pipe_oc8:dffpipe_ws_dgrp\|dffpipe_id9:dffpipe10\|dffe12a\[4\] 860 ps " "Info: Minimum slack time is 860 ps for clock \"fifo_pll:M3\|altpll:altpll_component\|_clk0\" between source register \"fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|alt_synch_pipe_oc8:dffpipe_ws_dgrp\|dffpipe_id9:dffpipe10\|dffe11a\[4\]\" and destination register \"fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|alt_synch_pipe_oc8:dffpipe_ws_dgrp\|dffpipe_id9:dffpipe10\|dffe12a\[4\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.651 ns + Shortest register register " "Info: + Shortest register to register delay is 0.651 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|alt_synch_pipe_oc8:dffpipe_ws_dgrp\|dffpipe_id9:dffpipe10\|dffe11a\[4\] 1 REG LC_X19_Y13_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y13_N2; Fanout = 1; REG Node = 'fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|alt_synch_pipe_oc8:dffpipe_ws_dgrp\|dffpipe_id9:dffpipe10\|dffe11a\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10|dffe11a[4] } "NODE_NAME" } } { "db/dffpipe_id9.tdf" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/db/dffpipe_id9.tdf" 32 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.536 ns) + CELL(0.115 ns) 0.651 ns fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|alt_synch_pipe_oc8:dffpipe_ws_dgrp\|dffpipe_id9:dffpipe10\|dffe12a\[4\] 2 REG LC_X19_Y13_N0 1 " "Info: 2: + IC(0.536 ns) + CELL(0.115 ns) = 0.651 ns; Loc. = LC_X19_Y13_N0; Fanout = 1; REG Node = 'fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|alt_synch_pipe_oc8:dffpipe_ws_dgrp\|dffpipe_id9:dffpipe10\|dffe12a\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.651 ns" { fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10|dffe11a[4] fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10|dffe12a[4] } "NODE_NAME" } } { "db/dffpipe_id9.tdf" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/db/dffpipe_id9.tdf" 33 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 17.67 % ) " "Info: Total cell delay = 0.115 ns ( 17.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.536 ns ( 82.33 % ) " "Info: Total interconnect delay = 0.536 ns ( 82.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.651 ns" { fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10|dffe11a[4] fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10|dffe12a[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.651 ns" { fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10|dffe11a[4] fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10|dffe12a[4] } { 0.000ns 0.536ns } { 0.000ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -1.885 ns " "Info: + Latch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination fifo_pll:M3\|altpll:altpll_component\|_clk0 25.000 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"fifo_pll:M3\|altpll:altpll_component\|_clk0\" is 25.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.885 ns " "Info: - Launch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source fifo_pll:M3\|altpll:altpll_component\|_clk0 25.000 ns -1.885 ns  50 " "Info: Clock period of Source clock \"fifo_pll:M3\|altpll:altpll_component\|_clk0\" is 25.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fifo_pll:M3\|altpll:altpll_component\|_clk0 destination 2.406 ns + Longest register " "Info: + Longest clock path from clock \"fifo_pll:M3\|altpll:altpll_component\|_clk0\" to destination register is 2.406 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifo_pll:M3\|altpll:altpll_component\|_clk0 1 CLK PLL_1 127 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 127; CLK Node = 'fifo_pll:M3\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fifo_pll:M3|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.695 ns) + CELL(0.711 ns) 2.406 ns fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|alt_synch_pipe_oc8:dffpipe_ws_dgrp\|dffpipe_id9:dffpipe10\|dffe12a\[4\] 2 REG LC_X19_Y13_N0 1 " "Info: 2: + IC(1.695 ns) + CELL(0.711 ns) = 2.406 ns; Loc. = LC_X19_Y13_N0; Fanout = 1; REG Node = 'fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|alt_synch_pipe_oc8:dffpipe_ws_dgrp\|dffpipe_id9:dffpipe10\|dffe12a\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10|dffe12a[4] } "NODE_NAME" } } { "db/dffpipe_id9.tdf" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/db/dffpipe_id9.tdf" 33 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.55 % ) " "Info: Total cell delay = 0.711 ns ( 29.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.695 ns ( 70.45 % ) " "Info: Total interconnect delay = 1.695 ns ( 70.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10|dffe12a[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10|dffe12a[4] } { 0.000ns 1.695ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fifo_pll:M3\|altpll:altpll_component\|_clk0 source 2.406 ns - Shortest register " "Info: - Shortest clock path from clock \"fifo_pll:M3\|altpll:altpll_component\|_clk0\" to source register is 2.406 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifo_pll:M3\|altpll:altpll_component\|_clk0 1 CLK PLL_1 127 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 127; CLK Node = 'fifo_pll:M3\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fifo_pll:M3|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.695 ns) + CELL(0.711 ns) 2.406 ns fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|alt_synch_pipe_oc8:dffpipe_ws_dgrp\|dffpipe_id9:dffpipe10\|dffe11a\[4\] 2 REG LC_X19_Y13_N2 1 " "Info: 2: + IC(1.695 ns) + CELL(0.711 ns) = 2.406 ns; Loc. = LC_X19_Y13_N2; Fanout = 1; REG Node = 'fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|alt_synch_pipe_oc8:dffpipe_ws_dgrp\|dffpipe_id9:dffpipe10\|dffe11a\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10|dffe11a[4] } "NODE_NAME" } } { "db/dffpipe_id9.tdf" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/db/dffpipe_id9.tdf" 32 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.55 % ) " "Info: Total cell delay = 0.711 ns ( 29.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.695 ns ( 70.45 % ) " "Info: Total interconnect delay = 1.695 ns ( 70.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10|dffe11a[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10|dffe11a[4] } { 0.000ns 1.695ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10|dffe12a[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10|dffe12a[4] } { 0.000ns 1.695ns } { 0.000ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10|dffe11a[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10|dffe11a[4] } { 0.000ns 1.695ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "db/dffpipe_id9.tdf" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/db/dffpipe_id9.tdf" 32 9 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "db/dffpipe_id9.tdf" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/db/dffpipe_id9.tdf" 33 9 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10|dffe12a[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10|dffe12a[4] } { 0.000ns 1.695ns } { 0.000ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10|dffe11a[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.406 ns" {