fifo.tan.qmsg

用VERILOG写的FIFO程序

{ "Info" "ITDB_FULL_SLACK_RESULT" "fifo_pll:M3\|altpll:altpll_component\|_clk1 memory fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|dpram_5ur:fiforam\|altsyncram_7mf1:altsyncram3\|ram_block4a0~portb_address_reg7 register rd_data\[5\] 43.226 ns " "Info: Slack time is 43.226 ns for clock \"fifo_pll:M3\|altpll:altpll_component\|_clk1\" between source memory \"fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|dpram_5ur:fiforam\|altsyncram_7mf1:altsyncram3\|ram_block4a0~portb_address_reg7\" and destination register \"rd_data\[5\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "147.62 MHz 6.774 ns " "Info: Fmax is 147.62 MHz (period= 6.774 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "49.327 ns + Largest memory register " "Info: + Largest memory to register requirement is 49.327 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "50.000 ns + " "Info: + Setup relationship between source and destination is 50.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 48.115 ns " "Info: + Latch edge is 48.115 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination fifo_pll:M3\|altpll:altpll_component\|_clk1 50.000 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"fifo_pll:M3\|altpll:altpll_component\|_clk1\" is 50.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.885 ns " "Info: - Launch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source fifo_pll:M3\|altpll:altpll_component\|_clk1 50.000 ns -1.885 ns  50 " "Info: Clock period of Source clock \"fifo_pll:M3\|altpll:altpll_component\|_clk1\" is 50.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.014 ns + Largest " "Info: + Largest clock skew is 0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fifo_pll:M3\|altpll:altpll_component\|_clk1 destination 2.406 ns + Shortest register " "Info: + Shortest clock path from clock \"fifo_pll:M3\|altpll:altpll_component\|_clk1\" to destination register is 2.406 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifo_pll:M3\|altpll:altpll_component\|_clk1 1 CLK PLL_1 105 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 105; CLK Node = 'fifo_pll:M3\|altpll:altpll_component\|_clk1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fifo_pll:M3|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.695 ns) + CELL(0.711 ns) 2.406 ns rd_data\[5\] 2 REG LC_X21_Y13_N5 1 " "Info: 2: + IC(1.695 ns) + CELL(0.711 ns) = 2.406 ns; Loc. = LC_X21_Y13_N5; Fanout = 1; REG Node = 'rd_data\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk1 rd_data[5] } "NODE_NAME" } } { "fifo.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo.v" 124 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.55 % ) " "Info: Total cell delay = 0.711 ns ( 29.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.695 ns ( 70.45 % ) " "Info: Total interconnect delay = 1.695 ns ( 70.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk1 rd_data[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk1 rd_data[5] } { 0.000ns 1.695ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fifo_pll:M3\|altpll:altpll_component\|_clk1 source 2.392 ns - Longest memory " "Info: - Longest clock path from clock \"fifo_pll:M3\|altpll:altpll_component\|_clk1\" to source memory is 2.392 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifo_pll:M3\|altpll:altpll_component\|_clk1 1 CLK PLL_1 105 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 105; CLK Node = 'fifo_pll:M3\|altpll:altpll_component\|_clk1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fifo_pll:M3|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.718 ns) 2.392 ns fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|dpram_5ur:fiforam\|altsyncram_7mf1:altsyncram3\|ram_block4a0~portb_address_reg7 2 MEM M4K_X17_Y12 8 " "Info: 2: + IC(1.674 ns) + CELL(0.718 ns) = 2.392 ns; Loc. = M4K_X17_Y12; Fanout = 8; MEM Node = 'fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|dpram_5ur:fiforam\|altsyncram_7mf1:altsyncram3\|ram_block4a0~portb_address_reg7'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.392 ns" { fifo_pll:M3|altpll:altpll_component|_clk1 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~portb_address_reg7 } "NODE_NAME" } } { "db/altsyncram_7mf1.tdf" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/db/altsyncram_7mf1.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.718 ns ( 30.02 % ) " "Info: Total cell delay = 0.718 ns ( 30.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.674 ns ( 69.98 % ) " "Info: Total interconnect delay = 1.674 ns ( 69.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.392 ns" { fifo_pll:M3|altpll:altpll_component|_clk1 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~portb_address_reg7 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.392 ns" { fifo_pll:M3|altpll:altpll_component|_clk1 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~portb_address_reg7 } { 0.000ns 1.674ns } { 0.000ns 0.718ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk1 rd_data[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk1 rd_data[5] } { 0.000ns 1.695ns } { 0.000ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.392 ns" { fifo_pll:M3|altpll:altpll_component|_clk1 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~portb_address_reg7 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.392 ns" { fifo_pll:M3|altpll:altpll_component|_clk1 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~portb_address_reg7 } { 0.000ns 1.674ns } { 0.000ns 0.718ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns - " "Info: - Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_7mf1.tdf" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/db/altsyncram_7mf1.tdf" 48 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "fifo.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo.v" 124 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk1 rd_data[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk1 rd_data[5] } { 0.000ns 1.695ns } { 0.000ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.392 ns" { fifo_pll:M3|altpll:altpll_component|_clk1 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~portb_address_reg7 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.392 ns" { fifo_pll:M3|altpll:altpll_component|_clk1 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~portb_address_reg7 } { 0.000ns 1.674ns } { 0.000ns 0.718ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.101 ns - Longest memory register " "Info: - Longest memory to register delay is 6.101 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|dpram_5ur:fiforam\|altsyncram_7mf1:altsyncram3\|ram_block4a0~portb_address_reg7 1 MEM M4K_X17_Y12 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y12; Fanout = 8; MEM Node = 'fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|dpram_5ur:fiforam\|altsyncram_7mf1:altsyncram3\|ram_block4a0~portb_address_reg7'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~portb_address_reg7 } "NODE_NAME" } } { "db/altsyncram_7mf1.tdf" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/db/altsyncram_7mf1.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.317 ns) 4.317 ns fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|dpram_5ur:fiforam\|altsyncram_7mf1:altsyncram3\|q_b\[5\] 2 MEM M4K_X17_Y12 1 " "Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X17_Y12; Fanout = 1; MEM Node = 'fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|dpram_5ur:fiforam\|altsyncram_7mf1:altsyncram3\|q_b\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.317 ns" { fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~portb_address_reg7 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|q_b[5] } "NODE_NAME" } } { "db/altsyncram_7mf1.tdf" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/db/altsyncram_7mf1.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.475 ns) + CELL(0.309 ns) 6.101 ns rd_data\[5\] 3 REG LC_X21_Y13_N5 1 " "Info: 3: + IC(1.475 ns) + CELL(0.309 ns) = 6.101 ns; Loc. = LC_X21_Y13_N5; Fanout = 1; REG Node = 'rd_data\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.784 ns" { fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|q_b[5] rd_data[5] } "NODE_NAME" } } { "fifo.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo.v" 124 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.626 ns ( 75.82 % ) " "Info: Total cell delay = 4.626 ns ( 75.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.475 ns ( 24.18 % ) " "Info: Total interconnect delay = 1.475 ns ( 24.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.101 ns" { fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~portb_address_reg7 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|q_b[5] rd_data[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.101 ns" { fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~portb_address_reg7 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|q_b[5] rd_data[5] } { 0.000ns 0.000ns 1.475ns } { 0.000ns 4.317ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk1 rd_data[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.406 ns" { fifo_pll:M3|altpll:altpll_component|_clk1 rd_data[5] } { 0.000ns 1.695ns } { 0.000ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.392 ns" { fifo_pll:M3|altpll:altpll_component|_clk1 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~portb_address_reg7 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.392 ns" { fifo_pll:M3|altpll:altpll_component|_clk1 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~portb_address_reg7 } { 0.000ns 1.674ns } { 0.000ns 0.718ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.101 ns" { fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~portb_address_reg7 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|q_b[5] rd_data[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.101 ns" { fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~portb_address_reg7 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|q_b[5] rd_data[5] } { 0.000ns 0.000ns 1.475ns } { 0.000ns 4.317ns 0.309ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clk register wr_data\[0\] register DISPLAY:M4\|display_data\[24\] 598 ps " "Info: Slack time is 598 ps for clock \"clk\" between source register \"wr_data\[0\]\" and destination register \"DISPLAY:M4\|display_data\[24\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "2.200 ns + Largest register register " "Info: + Largest register to register requirement is 2.200 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "1.885 ns + " "Info: + Setup relationship between source and destination is 1.885 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 3.115 ns " "Info: - Launch edge is 3.115 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source fifo_pll:M3\|altpll:altpll_component\|_clk0 25.000 ns -1.885 ns  50 " "Info: Clock period of Source clock \"fifo_pll:M3\|altpll:altpll_component\|_clk0\" is 25.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.576 ns + Largest " "Info: + Largest clock skew is 0.576 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.963 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.963 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 126 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 126; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.711 ns) 2.963 ns DISPLAY:M4\|display_data\[24\] 2 REG LC_X22_Y13_N4 1 " "Info: 2: + IC(0.783 ns) + CELL(0.711 ns) = 2.963 ns; Loc. = LC_X22_Y13_N4; Fanout = 1; REG Node = 'DISPLAY:M4\|display_data\[24\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.494 ns" { clk DISPLAY:M4|display_data[24] } "NODE_NAME" } } { "DISPLAY.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/DISPLAY.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.57 % ) " "Info: Total cell delay = 2.180 ns ( 73.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns ( 26.43 % ) " "Info: Total interconnect delay = 0.783 ns ( 26.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.963 ns" { clk DISPLAY:M4|display_data[24] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.963 ns" { clk clk~out0 DISPLAY:M4|display_data[24] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fifo_pll:M3\|altpll:altpll_component\|_clk0 source 2.387 ns - Longest register " "Info: - Longest clock path from clock \"fifo_pll:M3\|altpll:altpll_component\|_clk0\" to source register is 2.387 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifo_pll:M3\|altpll:altpll_component\|_clk0 1 CLK PLL_1 127 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 127; CLK Node = 'fifo_pll:M3\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fifo_pll:M3|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.676 ns) + CELL(0.711 ns) 2.387 ns wr_data\[0\] 2 REG LC_X21_Y12_N0 5 " "Info: 2: + IC(1.676 ns) + CELL(0.711 ns) = 2.387 ns; Loc. = LC_X21_Y12_N0; Fanout = 5; REG Node = 'wr_data\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.387 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 wr_data[0] } "NODE_NAME" } } { "fifo.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.79 % ) " "Info: Total cell delay = 0.711 ns ( 29.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.676 ns ( 70.21 % ) " "Info: Total interconnect delay = 1.676 ns ( 70.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.387 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 wr_data[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.387 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 wr_data[0] } { 0.000ns 1.676ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.963 ns" { clk DISPLAY:M4|display_data[24] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.963 ns" { clk clk~out0 DISPLAY:M4|display_data[24] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.387 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 wr_data[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.387 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 wr_data[0] } { 0.000ns 1.676ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "fifo.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo.v" 75 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "DISPLAY.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/DISPLAY.v" 88 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.963 ns" { clk DISPLAY:M4|display_data[24] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.963 ns" { clk clk~out0 DISPLAY:M4|display_data[24] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.387 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 wr_data[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.387 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 wr_data[0] } { 0.000ns 1.676ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.602 ns - Longest register register " "Info: - Longest register to register delay is 1.602 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wr_data\[0\] 1 REG LC_X21_Y12_N0 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y12_N0; Fanout = 5; REG Node = 'wr_data\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { wr_data[0] } "NODE_NAME" } } { "fifo.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.293 ns) + CELL(0.309 ns) 1.602 ns DISPLAY:M4\|display_data\[24\] 2 REG LC_X22_Y13_N4 1 " "Info: 2: + IC(1.293 ns) + CELL(0.309 ns) = 1.602 ns; Loc. = LC_X22_Y13_N4; Fanout = 1; REG Node = 'DISPLAY:M4\|display_data\[24\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.602 ns" { wr_data[0] DISPLAY:M4|display_data[24] } "NODE_NAME" } } { "DISPLAY.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/DISPLAY.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 19.29 % ) " "Info: Total cell delay = 0.309 ns ( 19.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.293 ns ( 80.71 % ) " "Info: Total interconnect delay = 1.293 ns ( 80.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.602 ns" { wr_data[0] DISPLAY:M4|display_data[24] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.602 ns" { wr_data[0] DISPLAY:M4|display_data[24] } { 0.000ns 1.293ns } { 0.000ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.963 ns" { clk DISPLAY:M4|display_data[24] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.963 ns" { clk clk~out0 DISPLAY:M4|display_data[24] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.387 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 wr_data[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.387 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 wr_data[0] } { 0.000ns 1.676ns } { 0.000ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.602 ns" { wr_data[0] DISPLAY:M4|display_data[24] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.602 ns" { wr_data[0] DISPLAY:M4|display_data[24] } { 0.000ns 1.293ns } { 0.000ns 0.309ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}