fifo.tan.qmsg

用VERILOG写的FIFO程序

{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "fifo_pll:M3\|altpll:altpll_component\|_clk0 memory fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|dpram_5ur:fiforam\|altsyncram_7mf1:altsyncram3\|ram_block4a0~porta_datain_reg7 memory fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|dpram_5ur:fiforam\|altsyncram_7mf1:altsyncram3\|ram_block4a0~porta_memory_reg7 19.924 ns " "Info: Slack time is 19.924 ns for clock \"fifo_pll:M3\|altpll:altpll_component\|_clk0\" between source memory \"fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|dpram_5ur:fiforam\|altsyncram_7mf1:altsyncram3\|ram_block4a0~porta_datain_reg7\" and destination memory \"fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|dpram_5ur:fiforam\|altsyncram_7mf1:altsyncram3\|ram_block4a0~porta_memory_reg7\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "197.01 MHz 5.076 ns " "Info: Fmax is 197.01 MHz (period= 5.076 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "24.243 ns + Largest memory memory " "Info: + Largest memory to memory requirement is 24.243 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "25.000 ns + " "Info: + Setup relationship between source and destination is 25.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 23.115 ns " "Info: + Latch edge is 23.115 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination fifo_pll:M3\|altpll:altpll_component\|_clk0 25.000 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"fifo_pll:M3\|altpll:altpll_component\|_clk0\" is 25.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.885 ns " "Info: - Launch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source fifo_pll:M3\|altpll:altpll_component\|_clk0 25.000 ns -1.885 ns  50 " "Info: Clock period of Source clock \"fifo_pll:M3\|altpll:altpll_component\|_clk0\" is 25.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns + Largest " "Info: + Largest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fifo_pll:M3\|altpll:altpll_component\|_clk0 destination 2.384 ns + Shortest memory " "Info: + Shortest clock path from clock \"fifo_pll:M3\|altpll:altpll_component\|_clk0\" to destination memory is 2.384 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifo_pll:M3\|altpll:altpll_component\|_clk0 1 CLK PLL_1 127 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 127; CLK Node = 'fifo_pll:M3\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fifo_pll:M3|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.676 ns) + CELL(0.708 ns) 2.384 ns fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|dpram_5ur:fiforam\|altsyncram_7mf1:altsyncram3\|ram_block4a0~porta_memory_reg7 2 MEM M4K_X17_Y12 0 " "Info: 2: + IC(1.676 ns) + CELL(0.708 ns) = 2.384 ns; Loc. = M4K_X17_Y12; Fanout = 0; MEM Node = 'fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|dpram_5ur:fiforam\|altsyncram_7mf1:altsyncram3\|ram_block4a0~porta_memory_reg7'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.384 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_memory_reg7 } "NODE_NAME" } } { "db/altsyncram_7mf1.tdf" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/db/altsyncram_7mf1.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.708 ns ( 29.70 % ) " "Info: Total cell delay = 0.708 ns ( 29.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.676 ns ( 70.30 % ) " "Info: Total interconnect delay = 1.676 ns ( 70.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.384 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_memory_reg7 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.384 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_memory_reg7 } { 0.000ns 1.676ns } { 0.000ns 0.708ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fifo_pll:M3\|altpll:altpll_component\|_clk0 source 2.398 ns - Longest memory " "Info: - Longest clock path from clock \"fifo_pll:M3\|altpll:altpll_component\|_clk0\" to source memory is 2.398 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifo_pll:M3\|altpll:altpll_component\|_clk0 1 CLK PLL_1 127 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 127; CLK Node = 'fifo_pll:M3\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fifo_pll:M3|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.676 ns) + CELL(0.722 ns) 2.398 ns fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|dpram_5ur:fiforam\|altsyncram_7mf1:altsyncram3\|ram_block4a0~porta_datain_reg7 2 MEM M4K_X17_Y12 1 " "Info: 2: + IC(1.676 ns) + CELL(0.722 ns) = 2.398 ns; Loc. = M4K_X17_Y12; Fanout = 1; MEM Node = 'fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|dpram_5ur:fiforam\|altsyncram_7mf1:altsyncram3\|ram_block4a0~porta_datain_reg7'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.398 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_datain_reg7 } "NODE_NAME" } } { "db/altsyncram_7mf1.tdf" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/db/altsyncram_7mf1.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.722 ns ( 30.11 % ) " "Info: Total cell delay = 0.722 ns ( 30.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.676 ns ( 69.89 % ) " "Info: Total interconnect delay = 1.676 ns ( 69.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.398 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_datain_reg7 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.398 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_datain_reg7 } { 0.000ns 1.676ns } { 0.000ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.384 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_memory_reg7 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.384 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_memory_reg7 } { 0.000ns 1.676ns } { 0.000ns 0.708ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.398 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_datain_reg7 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.398 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_datain_reg7 } { 0.000ns 1.676ns } { 0.000ns 0.722ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns - " "Info: - Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_7mf1.tdf" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/db/altsyncram_7mf1.tdf" 48 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns - " "Info: - Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_7mf1.tdf" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/db/altsyncram_7mf1.tdf" 48 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.384 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_memory_reg7 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.384 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_memory_reg7 } { 0.000ns 1.676ns } { 0.000ns 0.708ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.398 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_datain_reg7 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.398 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_datain_reg7 } { 0.000ns 1.676ns } { 0.000ns 0.722ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns - Longest memory memory " "Info: - Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|dpram_5ur:fiforam\|altsyncram_7mf1:altsyncram3\|ram_block4a0~porta_datain_reg7 1 MEM M4K_X17_Y12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y12; Fanout = 1; MEM Node = 'fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|dpram_5ur:fiforam\|altsyncram_7mf1:altsyncram3\|ram_block4a0~porta_datain_reg7'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_datain_reg7 } "NODE_NAME" } } { "db/altsyncram_7mf1.tdf" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/db/altsyncram_7mf1.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|dpram_5ur:fiforam\|altsyncram_7mf1:altsyncram3\|ram_block4a0~porta_memory_reg7 2 MEM M4K_X17_Y12 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X17_Y12; Fanout = 0; MEM Node = 'fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\|dpram_5ur:fiforam\|altsyncram_7mf1:altsyncram3\|ram_block4a0~porta_memory_reg7'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_datain_reg7 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_memory_reg7 } "NODE_NAME" } } { "db/altsyncram_7mf1.tdf" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/db/altsyncram_7mf1.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_datain_reg7 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_memory_reg7 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.319 ns" { fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_datain_reg7 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_memory_reg7 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.384 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_memory_reg7 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.384 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_memory_reg7 } { 0.000ns 1.676ns } { 0.000ns 0.708ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.398 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_datain_reg7 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.398 ns" { fifo_pll:M3|altpll:altpll_component|_clk0 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_datain_reg7 } { 0.000ns 1.676ns } { 0.000ns 0.722ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_datain_reg7 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_memory_reg7 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.319 ns" { fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_datain_reg7 fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3|ram_block4a0~porta_memory_reg7 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}