fifo.smp_dump.txt

用VERILOG写的FIFO程序

State Machine - |fifo|wr_state
Name wr_state.Wr_over wr_state.Wr_writing_c wr_state.Wr_writing_b wr_state.Wr_writing_a wr_state.Wr_idle 
wr_state.Wr_idle 0 0 0 0 0 
wr_state.Wr_writing_c 0 1 0 0 1 
wr_state.Wr_writing_b 0 0 1 0 1 
wr_state.Wr_writing_a 0 0 0 1 1 
wr_state.Wr_over 1 0 0 0 1 

State Machine - |fifo|rd_state
Name rd_state.Rd_over rd_state.Rd_reading_c rd_state.Rd_reading_b rd_state.Rd_reading_a rd_state.Rd_idle 
rd_state.Rd_idle 0 0 0 0 0 
rd_state.Rd_reading_c 0 1 0 0 1 
rd_state.Rd_reading_b 0 0 1 0 1 
rd_state.Rd_reading_a 0 0 0 1 1 
rd_state.Rd_over 1 0 0 0 1 

State Machine - |fifo|DISPLAY:M4|state
Name state.CH451_Display_temp state.CH451_Display state.CH451_Display_ready state.CH451_Get_data state.CH451_Open_display state.CH451_Set_display_mode state.CH451_Reset state.CH451_Enable_serial_port state.CH451_Idle 
state.CH451_Idle 0 0 0 0 0 0 0 0 0 
state.CH451_Display 0 1 0 0 0 0 0 0 1 
state.CH451_Display_ready 0 0 1 0 0 0 0 0 1 
state.CH451_Get_data 0 0 0 1 0 0 0 0 1 
state.CH451_Open_display 0 0 0 0 1 0 0 0 1 
state.CH451_Set_display_mode 0 0 0 0 0 1 0 0 1 
state.CH451_Reset 0 0 0 0 0 0 1 0 1 
state.CH451_Enable_serial_port 0 0 0 0 0 0 0 1 1 
state.CH451_Display_temp 1 0 0 0 0 0 0 0 1 

State Machine - |fifo|DISPLAY:M4|shift_state
Name shift_state.Pull_up_ch451_load shift_state.Shift_paralell_data shift_state.Pull_up_ch451_dclk shift_state.Pull_down_ch451_dclk shift_state.Get_shift_out_data shift_state.Pull_down_ch451_load shift_state.Shift12_out_idle 
shift_state.Shift12_out_idle 0 0 0 0 0 0 0 
shift_state.Shift_paralell_data 0 1 0 0 0 0 1 
shift_state.Pull_up_ch451_dclk 0 0 1 0 0 0 1 
shift_state.Pull_down_ch451_dclk 0 0 0 1 0 0 1 
shift_state.Get_shift_out_data 0 0 0 0 1 0 1 
shift_state.Pull_down_ch451_load 0 0 0 0 0 1 1 
shift_state.Pull_up_ch451_load 1 0 0 0 0 0 1