alt_synch_pipe_nc8.tdf

用VERILOG写的FIFO程序

--dffpipe DELAY=3 WIDTH=8 clock clrn d q ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF
--VERSION_BEGIN 6.0 cbx_a_gray2bin 2006:02:28:17:43:38:SJ cbx_a_graycounter 2006:03:13:11:03:08:SJ cbx_altdpram 2006:01:09:10:52:42:SJ cbx_altsyncram 2006:03:30:14:59:04:SJ cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_dcfifo 2006:06:14:15:40:04:SJ cbx_fifo_common 2006:01:09:11:23:34:SJ cbx_flex10ke 2006:01:09:11:13:48:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_compare 2006:01:09:11:15:40:SJ cbx_lpm_counter 2006:03:23:14:19:24:SJ cbx_lpm_decode 2006:01:09:11:16:44:SJ cbx_lpm_mux 2006:01:09:11:16:16:SJ cbx_mgl 2006:05:17:10:06:16:SJ cbx_scfifo 2006:01:09:11:24:10:SJ cbx_stratix 2006:05:17:09:28:32:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


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FUNCTION dffpipe_hd9 (clock, clrn, d[7..0])
RETURNS ( q[7..0]);

--synthesis_resources = lut 24 
OPTIONS ALTERA_INTERNAL_OPTION = "X_ON_VIOLATION_OPTION=OFF";

SUBDESIGN alt_synch_pipe_nc8
( 
	clock	:	input;
	clrn	:	input;
	d[7..0]	:	input;
	q[7..0]	:	output;
) 
VARIABLE 
	dffpipe6 : dffpipe_hd9;

BEGIN 
	dffpipe6.clock = clock;
	dffpipe6.clrn = clrn;
	dffpipe6.d[] = d[];
	q[] = dffpipe6.q[];
END;
--VALID FILE