dffpipe_id9.tdf

用VERILOG写的FIFO程序

--dffpipe DELAY=3 WIDTH=8 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 6.0 cbx_mgl 2006:05:17:10:06:16:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


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--synthesis_resources = lut 24 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";

SUBDESIGN dffpipe_id9
( 
	clock	:	input;
	clrn	:	input;
	d[7..0]	:	input;
	q[7..0]	:	output;
) 
VARIABLE 
	dffe11a[7..0] : dffe;
	dffe12a[7..0] : dffe;
	dffe13a[7..0] : dffe;
	ena	: NODE;
	prn	: NODE;
	sclr	: NODE;

BEGIN 
	dffe11a[].CLK = clock;
	dffe11a[].CLRN = clrn;
	dffe11a[].D = (d[] & (! sclr));
	dffe11a[].ENA = ena;
	dffe11a[].PRN = prn;
	dffe12a[].CLK = clock;
	dffe12a[].CLRN = clrn;
	dffe12a[].D = (dffe11a[].Q & (! sclr));
	dffe12a[].ENA = ena;
	dffe12a[].PRN = prn;
	dffe13a[].CLK = clock;
	dffe13a[].CLRN = clrn;
	dffe13a[].D = (dffe12a[].Q & (! sclr));
	dffe13a[].ENA = ena;
	dffe13a[].PRN = prn;
	ena = VCC;
	prn = VCC;
	q[] = dffe13a[].Q;
	sclr = GND;
END;
--VALID FILE