fifo.map.qmsg

用VERILOG写的FIFO程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 18 15:54:32 2008 " "Info: Processing started: Sun May 18 15:54:32 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fifo -c fifo " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fifo -c fifo" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fifo.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo " "Info: Found entity 1: fifo" {  } { { "fifo.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system_rst.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file system_rst.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_rst " "Info: Found entity 1: system_rst" {  } { { "system_rst.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/system_rst.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IVRFX_VERI_OBJ_DIFF_ONLY_IN_CASE" "CH451_DISPLAY CH451_Display DISPLAY.v(32) " "Info (10281): Verilog HDL Declaration information at DISPLAY.v(32): object \"CH451_DISPLAY\" differs only in case from object \"CH451_Display\" in the same scope" {  } { { "DISPLAY.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/DISPLAY.v" 32 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "CH451_Display DISPLAY.v(42) " "Info (10151): Verilog HDL Declaration information at DISPLAY.v(42): \"CH451_Display\" is declared here" {  } { { "DISPLAY.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/DISPLAY.v" 42 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DISPLAY.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DISPLAY.v" { { "Info" "ISGN_ENTITY_NAME" "1 DISPLAY " "Info: Found entity 1: DISPLAY" {  } { { "DISPLAY.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/DISPLAY.v" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "fifo " "Info: Elaborating entity \"fifo\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "fifo_ram.v 1 1 " "Warning: Using design file fifo_ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_ram " "Info: Found entity 1: fifo_ram" {  } { { "fifo_ram.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo_ram.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fifo_ram fifo_ram:M1 " "Info: Elaborating entity \"fifo_ram\" for hierarchy \"fifo_ram:M1\"" {  } { { "fifo.v" "M1" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo.v" 153 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus60/libraries/megafunctions/dcfifo.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/dcfifo.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dcfifo " "Info: Found entity 1: dcfifo" {  } { { "dcfifo.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/dcfifo.tdf" 107 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo fifo_ram:M1\|dcfifo:dcfifo_component " "Info: Elaborating entity \"dcfifo\" for hierarchy \"fifo_ram:M1\|dcfifo:dcfifo_component\"" {  } { { "fifo_ram.v" "dcfifo_component" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo_ram.v" 79 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "fifo_ram:M1\|dcfifo:dcfifo_component " "Info: Elaborated megafunction instantiation \"fifo_ram:M1\|dcfifo:dcfifo_component\"" {  } { { "fifo_ram.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo_ram.v" 79 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dcfifo_et91.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dcfifo_et91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dcfifo_et91 " "Info: Found entity 1: dcfifo_et91" {  } { { "db/dcfifo_et91.tdf" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/db/dcfifo_et91.tdf" 44 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo_et91 fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated " "Info: Elaborating entity \"dcfifo_et91\" for hierarchy \"fifo_ram:M1\|dcfifo:dcfifo_component\|dcfifo_et91:auto_generated\"" {  } { { "dcfifo.tdf" "auto_generated" { Text "d:/altera/quartus60/libraries/megafunctions/dcfifo.tdf" 187 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_gtc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_gtc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_gtc " "Info: Found entity 1: a_fefifo_gtc" {  } { { "db/a_fefifo_gtc.tdf" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/db/a_fefifo_gtc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}