fifo.hier_info

用VERILOG写的FIFO程序

result[0] <= add_sub_cella[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= add_sub_cella[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= add_sub_cella[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= add_sub_cella[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= add_sub_cella[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= add_sub_cella[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= add_sub_cella[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= add_sub_cella[7].DB_MAX_OUTPUT_PORT_TYPE


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|add_sub_fub:lpm_add_sub_wr_udwn
datab[0] => datab_node[0].IN0
datab[1] => datab_node[1].IN0
datab[2] => datab_node[2].IN0
datab[3] => datab_node[3].IN0
datab[4] => datab_node[4].IN0
datab[5] => datab_node[5].IN0
datab[6] => datab_node[6].IN0
datab[7] => datab_node[7].IN0
result[0] <= add_sub_cella[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= add_sub_cella[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= add_sub_cella[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= add_sub_cella[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= add_sub_cella[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= add_sub_cella[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= add_sub_cella[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= add_sub_cella[7].DB_MAX_OUTPUT_PORT_TYPE


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|cntr_9v7:rdptr_b
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
aclr => counter_cella4.ACLR
aclr => counter_cella5.ACLR
aclr => counter_cella6.ACLR
aclr => counter_cella7.ACLR
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
cnt_en => counter_cella0.DATAB
cnt_en => counter_cella1.DATAB
cnt_en => counter_cella2.DATAB
cnt_en => counter_cella3.DATAB
cnt_en => counter_cella4.DATAB
cnt_en => counter_cella5.DATAB
cnt_en => counter_cella6.DATAB
cnt_en => counter_cella7.DATAB
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|cntr_9v7:wrptr_b
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
aclr => counter_cella4.ACLR
aclr => counter_cella5.ACLR
aclr => counter_cella6.ACLR
aclr => counter_cella7.ACLR
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
cnt_en => counter_cella0.DATAB
cnt_en => counter_cella1.DATAB
cnt_en => counter_cella2.DATAB
cnt_en => counter_cella3.DATAB
cnt_en => counter_cella4.DATAB
cnt_en => counter_cella5.DATAB
cnt_en => counter_cella6.DATAB
cnt_en => counter_cella7.DATAB
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT


|fifo|system_rst:M2
clk => counter[6].CLK
clk => counter[5].CLK
clk => counter[4].CLK
clk => counter[3].CLK
clk => counter[2].CLK
clk => counter[1].CLK
clk => counter[0].CLK
clk => system_rst~reg0.CLK
clk => counter[7].CLK
rst_n => counter[6].ACLR
rst_n => counter[5].ACLR
rst_n => counter[4].ACLR
rst_n => counter[3].ACLR
rst_n => counter[2].ACLR
rst_n => counter[1].ACLR
rst_n => counter[0].ACLR
rst_n => system_rst~reg0.ACLR
rst_n => counter[7].ACLR
system_rst <= system_rst~reg0.DB_MAX_OUTPUT_PORT_TYPE


|fifo|fifo_pll:M3
inclk0 => sub_wire4[0].IN1
c0 <= altpll:altpll_component.clk
c1 <= altpll:altpll_component.clk


|fifo|fifo_pll:M3|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => pll.ENA2
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= pll.CLK1
clk[2] <= pll.CLK2
clk[3] <= <UNC>
clk[4] <= <UNC>
clk[5] <= <UNC>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE


|fifo|DISPLAY:M4
clk => clk_div_counter[2].CLK
clk => clk_div_counter[1].CLK
clk => clk_div_counter[0].CLK
clk => CH451_DIN~reg0.CLK
clk => CH451_DCLK~reg0.CLK
clk => CH451_LOAD~reg0.CLK
clk => transfer_count[2].CLK
clk => transfer_count[1].CLK
clk => transfer_count[0].CLK
clk => shift_counter[3].CLK
clk => shift_counter[2].CLK
clk => shift_counter[1].CLK
clk => shift_counter[0].CLK
clk => display_data[31].CLK
clk => display_data[30].CLK
clk => display_data[29].CLK
clk => display_data[28].CLK
clk => display_data[27].CLK
clk => display_data[26].CLK
clk => display_data[25].CLK
clk => display_data[24].CLK
clk => display_data[23].CLK
clk => display_data[22].CLK
clk => display_data[21].CLK
clk => display_data[20].CLK
clk => display_data[19].CLK
clk => display_data[18].CLK
clk => display_data[17].CLK
clk => display_data[16].CLK
clk => display_data[15].CLK
clk => display_data[14].CLK
clk => display_data[13].CLK
clk => display_data[12].CLK
clk => display_data[11].CLK
clk => display_data[10].CLK
clk => display_data[9].CLK
clk => display_data[8].CLK
clk => display_data[7].CLK
clk => display_data[6].CLK
clk => display_data[5].CLK
clk => display_data[4].CLK
clk => display_data[3].CLK
clk => display_data[2].CLK
clk => display_data[1].CLK
clk => display_data[0].CLK
clk => decemial_point_sel[7].CLK
clk => decemial_point_sel[6].CLK
clk => decemial_point_sel[5].CLK
clk => decemial_point_sel[4].CLK
clk => decemial_point_sel[3].CLK
clk => decemial_point_sel[2].CLK
clk => decemial_point_sel[1].CLK
clk => decemial_point_sel[0].CLK
clk => display_led_sel[31].CLK
clk => display_led_sel[30].CLK
clk => display_led_sel[29].CLK
clk => display_led_sel[28].CLK
clk => display_led_sel[27].CLK
clk => display_led_sel[26].CLK
clk => display_led_sel[25].CLK
clk => display_led_sel[24].CLK
clk => display_led_sel[23].CLK
clk => display_led_sel[22].CLK
clk => display_led_sel[21].CLK
clk => display_led_sel[20].CLK
clk => display_led_sel[19].CLK
clk => display_led_sel[18].CLK
clk => display_led_sel[17].CLK
clk => display_led_sel[16].CLK
clk => display_led_sel[15].CLK
clk => display_led_sel[14].CLK
clk => display_led_sel[13].CLK
clk => display_led_sel[12].CLK
clk => display_led_sel[11].CLK
clk => display_led_sel[10].CLK
clk => display_led_sel[9].CLK
clk => display_led_sel[8].CLK
clk => display_led_sel[7].CLK
clk => display_led_sel[6].CLK
clk => display_led_sel[5].CLK
clk => display_led_sel[4].CLK
clk => display_led_sel[3].CLK
clk => display_led_sel[2].CLK
clk => display_led_sel[1].CLK
clk => display_led_sel[0].CLK
clk => CH451_cmd[11].CLK
clk => CH451_cmd[10].CLK
clk => CH451_cmd[9].CLK
clk => CH451_cmd[8].CLK
clk => CH451_cmd[7].CLK
clk => CH451_cmd[6].CLK
clk => CH451_cmd[5].CLK
clk => CH451_cmd[4].CLK
clk => CH451_cmd[3].CLK
clk => CH451_cmd[2].CLK
clk => CH451_cmd[1].CLK
clk => CH451_cmd[0].CLK
clk => trans_over_flag.CLK
clk => clk_div_counter[3].CLK
clk => state~22.IN1
clk => shift_state~15.IN1
rst_n => CH451_DIN~reg0.PRESET
rst_n => CH451_DCLK~reg0.PRESET
rst_n => CH451_LOAD~reg0.PRESET
rst_n => transfer_count[2].ACLR
rst_n => transfer_count[1].ACLR
rst_n => transfer_count[0].ACLR
rst_n => shift_counter[3].ACLR
rst_n => shift_counter[2].ACLR
rst_n => shift_counter[1].ACLR
rst_n => shift_counter[0].ACLR
rst_n => display_data[31].ACLR
rst_n => display_data[30].ACLR
rst_n => display_data[29].ACLR
rst_n => display_data[28].ACLR
rst_n => display_data[27].ACLR
rst_n => display_data[26].ACLR
rst_n => display_data[25].ACLR
rst_n => display_data[24].ACLR
rst_n => display_data[23].ACLR
rst_n => display_data[22].ACLR
rst_n => display_data[21].ACLR
rst_n => display_data[20].ACLR
rst_n => display_data[19].ACLR
rst_n => display_data[18].ACLR
rst_n => display_data[17].ACLR
rst_n => display_data[16].ACLR
rst_n => display_data[15].ACLR
rst_n => display_data[14].ACLR
rst_n => display_data[13].ACLR
rst_n => display_data[12].ACLR
rst_n => display_data[11].ACLR
rst_n => display_data[10].ACLR
rst_n => display_data[9].ACLR
rst_n => display_data[8].ACLR
rst_n => display_data[7].ACLR
rst_n => display_data[6].ACLR
rst_n => display_data[5].ACLR
rst_n => display_data[4].ACLR
rst_n => display_data[3].ACLR
rst_n => display_data[2].ACLR
rst_n => display_data[1].ACLR
rst_n => display_data[0].ACLR
rst_n => decemial_point_sel[7].ACLR
rst_n => decemial_point_sel[6].ACLR
rst_n => decemial_point_sel[5].ACLR
rst_n => decemial_point_sel[4].ACLR
rst_n => decemial_point_sel[3].ACLR
rst_n => decemial_point_sel[2].ACLR
rst_n => decemial_point_sel[1].ACLR
rst_n => decemial_point_sel[0].ACLR
rst_n => display_led_sel[31].ACLR
rst_n => display_led_sel[30].ACLR
rst_n => display_led_sel[29].ACLR
rst_n => display_led_sel[28].ACLR
rst_n => display_led_sel[27].ACLR
rst_n => display_led_sel[26].ACLR
rst_n => display_led_sel[25].ACLR
rst_n => display_led_sel[24].ACLR
rst_n => display_led_sel[23].ACLR
rst_n => display_led_sel[22].ACLR
rst_n => display_led_sel[21].ACLR
rst_n => display_led_sel[20].ACLR
rst_n => display_led_sel[19].ACLR
rst_n => display_led_sel[18].ACLR
rst_n => display_led_sel[17].ACLR
rst_n => display_led_sel[16].ACLR
rst_n => display_led_sel[15].ACLR
rst_n => display_led_sel[14].ACLR
rst_n => display_led_sel[13].ACLR
rst_n => display_led_sel[12].ACLR
rst_n => display_led_sel[11].ACLR
rst_n => display_led_sel[10].ACLR
rst_n => display_led_sel[9].ACLR
rst_n => display_led_sel[8].ACLR
rst_n => display_led_sel[7].ACLR
rst_n => display_led_sel[6].ACLR
rst_n => display_led_sel[5].ACLR
rst_n => display_led_sel[4].ACLR
rst_n => display_led_sel[3].ACLR
rst_n => display_led_sel[2].ACLR
rst_n => display_led_sel[1].ACLR
rst_n => display_led_sel[0].ACLR
rst_n => CH451_cmd[11].ACLR
rst_n => CH451_cmd[10].ACLR
rst_n => CH451_cmd[9].ACLR
rst_n => CH451_cmd[8].ACLR
rst_n => CH451_cmd[7].ACLR
rst_n => CH451_cmd[6].ACLR
rst_n => CH451_cmd[5].ACLR
rst_n => CH451_cmd[4].ACLR
rst_n => CH451_cmd[3].ACLR
rst_n => CH451_cmd[2].ACLR
rst_n => CH451_cmd[1].ACLR
rst_n => CH451_cmd[0].ACLR
rst_n => trans_over_flag.ACLR
rst_n => clk_div_counter[2].ACLR
rst_n => clk_div_counter[1].ACLR
rst_n => clk_div_counter[0].ACLR
rst_n => clk_div_counter[3].ACLR
rst_n => state~23.IN1
rst_n => shift_state~16.IN1
data[0] => Selector70.IN2
data[1] => Selector69.IN2
data[2] => Selector68.IN2
data[3] => Selector67.IN2
data[4] => Selector66.IN2
data[5] => Selector65.IN2
data[6] => Selector64.IN2
data[7] => Selector63.IN2
data[8] => Selector62.IN2
data[9] => Selector61.IN2
data[10] => Selector60.IN2
data[11] => Selector59.IN2
data[12] => Selector58.IN2
data[13] => Selector57.IN2
data[14] => Selector56.IN2
data[15] => Selector55.IN2
data[16] => Selector54.IN2
data[17] => Selector53.IN2
data[18] => Selector52.IN2
data[19] => Selector51.IN2
data[20] => Selector50.IN2
data[21] => Selector49.IN2
data[22] => Selector48.IN2
data[23] => Selector47.IN2
data[24] => Selector46.IN2
data[25] => Selector45.IN2
data[26] => Selector44.IN2
data[27] => Selector43.IN2
data[28] => Selector42.IN2
data[29] => Selector41.IN2
data[30] => Selector40.IN2
data[31] => Selector39.IN2
CH451_DCLK <= CH451_DCLK~reg0.DB_MAX_OUTPUT_PORT_TYPE
CH451_DIN <= CH451_DIN~reg0.DB_MAX_OUTPUT_PORT_TYPE
CH451_LOAD <= CH451_LOAD~reg0.DB_MAX_OUTPUT_PORT_TYPE