fifo.hier_info

用VERILOG写的FIFO程序

address_b[3] => ram_block4a6.PORTBADDR3
address_b[3] => ram_block4a7.PORTBADDR3
address_b[4] => ram_block4a0.PORTBADDR4
address_b[4] => ram_block4a1.PORTBADDR4
address_b[4] => ram_block4a2.PORTBADDR4
address_b[4] => ram_block4a3.PORTBADDR4
address_b[4] => ram_block4a4.PORTBADDR4
address_b[4] => ram_block4a5.PORTBADDR4
address_b[4] => ram_block4a6.PORTBADDR4
address_b[4] => ram_block4a7.PORTBADDR4
address_b[5] => ram_block4a0.PORTBADDR5
address_b[5] => ram_block4a1.PORTBADDR5
address_b[5] => ram_block4a2.PORTBADDR5
address_b[5] => ram_block4a3.PORTBADDR5
address_b[5] => ram_block4a4.PORTBADDR5
address_b[5] => ram_block4a5.PORTBADDR5
address_b[5] => ram_block4a6.PORTBADDR5
address_b[5] => ram_block4a7.PORTBADDR5
address_b[6] => ram_block4a0.PORTBADDR6
address_b[6] => ram_block4a1.PORTBADDR6
address_b[6] => ram_block4a2.PORTBADDR6
address_b[6] => ram_block4a3.PORTBADDR6
address_b[6] => ram_block4a4.PORTBADDR6
address_b[6] => ram_block4a5.PORTBADDR6
address_b[6] => ram_block4a6.PORTBADDR6
address_b[6] => ram_block4a7.PORTBADDR6
address_b[7] => ram_block4a0.PORTBADDR7
address_b[7] => ram_block4a1.PORTBADDR7
address_b[7] => ram_block4a2.PORTBADDR7
address_b[7] => ram_block4a3.PORTBADDR7
address_b[7] => ram_block4a4.PORTBADDR7
address_b[7] => ram_block4a5.PORTBADDR7
address_b[7] => ram_block4a6.PORTBADDR7
address_b[7] => ram_block4a7.PORTBADDR7
clock0 => ram_block4a0.CLK0
clock0 => ram_block4a1.CLK0
clock0 => ram_block4a2.CLK0
clock0 => ram_block4a3.CLK0
clock0 => ram_block4a4.CLK0
clock0 => ram_block4a5.CLK0
clock0 => ram_block4a6.CLK0
clock0 => ram_block4a7.CLK0
clock1 => ram_block4a0.CLK1
clock1 => ram_block4a1.CLK1
clock1 => ram_block4a2.CLK1
clock1 => ram_block4a3.CLK1
clock1 => ram_block4a4.CLK1
clock1 => ram_block4a5.CLK1
clock1 => ram_block4a6.CLK1
clock1 => ram_block4a7.CLK1
clocken1 => ram_block4a0.ENA1
clocken1 => ram_block4a1.ENA1
clocken1 => ram_block4a2.ENA1
clocken1 => ram_block4a3.ENA1
clocken1 => ram_block4a4.ENA1
clocken1 => ram_block4a5.ENA1
clocken1 => ram_block4a6.ENA1
clocken1 => ram_block4a7.ENA1
data_a[0] => ram_block4a0.PORTADATAIN
data_a[1] => ram_block4a1.PORTADATAIN
data_a[2] => ram_block4a2.PORTADATAIN
data_a[3] => ram_block4a3.PORTADATAIN
data_a[4] => ram_block4a4.PORTADATAIN
data_a[5] => ram_block4a5.PORTADATAIN
data_a[6] => ram_block4a6.PORTADATAIN
data_a[7] => ram_block4a7.PORTADATAIN
q_b[0] <= ram_block4a0.PORTBDATAOUT
q_b[1] <= ram_block4a1.PORTBDATAOUT
q_b[2] <= ram_block4a2.PORTBDATAOUT
q_b[3] <= ram_block4a3.PORTBDATAOUT
q_b[4] <= ram_block4a4.PORTBDATAOUT
q_b[5] <= ram_block4a5.PORTBDATAOUT
q_b[6] <= ram_block4a6.PORTBDATAOUT
q_b[7] <= ram_block4a7.PORTBDATAOUT
wren_a => ram_block4a0.ENA0
wren_a => ram_block4a1.ENA0
wren_a => ram_block4a2.ENA0
wren_a => ram_block4a3.ENA0
wren_a => ram_block4a4.ENA0
wren_a => ram_block4a5.ENA0
wren_a => ram_block4a6.ENA0
wren_a => ram_block4a7.ENA0


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dffpipe_fd9:dffpipe_rdbuw
clock => dffe5a[7].CLK
clock => dffe5a[6].CLK
clock => dffe5a[5].CLK
clock => dffe5a[4].CLK
clock => dffe5a[3].CLK
clock => dffe5a[2].CLK
clock => dffe5a[1].CLK
clock => dffe5a[0].CLK
clrn => dffe5a[7].ACLR
clrn => dffe5a[6].ACLR
clrn => dffe5a[5].ACLR
clrn => dffe5a[4].ACLR
clrn => dffe5a[3].ACLR
clrn => dffe5a[2].ACLR
clrn => dffe5a[1].ACLR
clrn => dffe5a[0].ACLR
q[0] <= dffe5a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffe5a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffe5a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffe5a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffe5a[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffe5a[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffe5a[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffe5a[7].DB_MAX_OUTPUT_PORT_TYPE


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dffpipe_fd9:dffpipe_rdusedw
clock => dffe5a[7].CLK
clock => dffe5a[6].CLK
clock => dffe5a[5].CLK
clock => dffe5a[4].CLK
clock => dffe5a[3].CLK
clock => dffe5a[2].CLK
clock => dffe5a[1].CLK
clock => dffe5a[0].CLK
clrn => dffe5a[7].ACLR
clrn => dffe5a[6].ACLR
clrn => dffe5a[5].ACLR
clrn => dffe5a[4].ACLR
clrn => dffe5a[3].ACLR
clrn => dffe5a[2].ACLR
clrn => dffe5a[1].ACLR
clrn => dffe5a[0].ACLR
q[0] <= dffe5a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffe5a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffe5a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffe5a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffe5a[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffe5a[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffe5a[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffe5a[7].DB_MAX_OUTPUT_PORT_TYPE


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dffpipe_fd9:dffpipe_rs_dbwp
clock => dffe5a[7].CLK
clock => dffe5a[6].CLK
clock => dffe5a[5].CLK
clock => dffe5a[4].CLK
clock => dffe5a[3].CLK
clock => dffe5a[2].CLK
clock => dffe5a[1].CLK
clock => dffe5a[0].CLK
clrn => dffe5a[7].ACLR
clrn => dffe5a[6].ACLR
clrn => dffe5a[5].ACLR
clrn => dffe5a[4].ACLR
clrn => dffe5a[3].ACLR
clrn => dffe5a[2].ACLR
clrn => dffe5a[1].ACLR
clrn => dffe5a[0].ACLR
q[0] <= dffe5a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffe5a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffe5a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffe5a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffe5a[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffe5a[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffe5a[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffe5a[7].DB_MAX_OUTPUT_PORT_TYPE


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_nc8:dffpipe_rs_dgwp
clock => dffpipe_hd9:dffpipe6.clock
clrn => dffpipe_hd9:dffpipe6.clrn
d[0] => dffpipe_hd9:dffpipe6.d[0]
d[1] => dffpipe_hd9:dffpipe6.d[1]
d[2] => dffpipe_hd9:dffpipe6.d[2]
d[3] => dffpipe_hd9:dffpipe6.d[3]
d[4] => dffpipe_hd9:dffpipe6.d[4]
d[5] => dffpipe_hd9:dffpipe6.d[5]
d[6] => dffpipe_hd9:dffpipe6.d[6]
d[7] => dffpipe_hd9:dffpipe6.d[7]
q[0] <= dffpipe_hd9:dffpipe6.q[0]
q[1] <= dffpipe_hd9:dffpipe6.q[1]
q[2] <= dffpipe_hd9:dffpipe6.q[2]
q[3] <= dffpipe_hd9:dffpipe6.q[3]
q[4] <= dffpipe_hd9:dffpipe6.q[4]
q[5] <= dffpipe_hd9:dffpipe6.q[5]
q[6] <= dffpipe_hd9:dffpipe6.q[6]
q[7] <= dffpipe_hd9:dffpipe6.q[7]


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_nc8:dffpipe_rs_dgwp|dffpipe_hd9:dffpipe6
clock => dffe7a[7].CLK
clock => dffe7a[6].CLK
clock => dffe7a[5].CLK
clock => dffe7a[4].CLK
clock => dffe7a[3].CLK
clock => dffe7a[2].CLK
clock => dffe7a[1].CLK
clock => dffe7a[0].CLK
clock => dffe8a[7].CLK
clock => dffe8a[6].CLK
clock => dffe8a[5].CLK
clock => dffe8a[4].CLK
clock => dffe8a[3].CLK
clock => dffe8a[2].CLK
clock => dffe8a[1].CLK
clock => dffe8a[0].CLK
clock => dffe9a[7].CLK
clock => dffe9a[6].CLK
clock => dffe9a[5].CLK
clock => dffe9a[4].CLK
clock => dffe9a[3].CLK
clock => dffe9a[2].CLK
clock => dffe9a[1].CLK
clock => dffe9a[0].CLK
clrn => dffe7a[7].ACLR
clrn => dffe7a[6].ACLR
clrn => dffe7a[5].ACLR
clrn => dffe7a[4].ACLR
clrn => dffe7a[3].ACLR
clrn => dffe7a[2].ACLR
clrn => dffe7a[1].ACLR
clrn => dffe7a[0].ACLR
clrn => dffe8a[7].ACLR
clrn => dffe8a[6].ACLR
clrn => dffe8a[5].ACLR
clrn => dffe8a[4].ACLR
clrn => dffe8a[3].ACLR
clrn => dffe8a[2].ACLR
clrn => dffe8a[1].ACLR
clrn => dffe8a[0].ACLR
clrn => dffe9a[7].ACLR
clrn => dffe9a[6].ACLR
clrn => dffe9a[5].ACLR
clrn => dffe9a[4].ACLR
clrn => dffe9a[3].ACLR
clrn => dffe9a[2].ACLR
clrn => dffe9a[1].ACLR
clrn => dffe9a[0].ACLR
q[0] <= dffe9a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffe9a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffe9a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffe9a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffe9a[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffe9a[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffe9a[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffe9a[7].DB_MAX_OUTPUT_PORT_TYPE


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dffpipe_fd9:dffpipe_wr_dbuw
clock => dffe5a[7].CLK
clock => dffe5a[6].CLK
clock => dffe5a[5].CLK
clock => dffe5a[4].CLK
clock => dffe5a[3].CLK
clock => dffe5a[2].CLK
clock => dffe5a[1].CLK
clock => dffe5a[0].CLK
clrn => dffe5a[7].ACLR
clrn => dffe5a[6].ACLR
clrn => dffe5a[5].ACLR
clrn => dffe5a[4].ACLR
clrn => dffe5a[3].ACLR
clrn => dffe5a[2].ACLR
clrn => dffe5a[1].ACLR
clrn => dffe5a[0].ACLR
q[0] <= dffe5a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffe5a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffe5a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffe5a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffe5a[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffe5a[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffe5a[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffe5a[7].DB_MAX_OUTPUT_PORT_TYPE


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dffpipe_fd9:dffpipe_wrusedw
clock => dffe5a[7].CLK
clock => dffe5a[6].CLK
clock => dffe5a[5].CLK
clock => dffe5a[4].CLK
clock => dffe5a[3].CLK
clock => dffe5a[2].CLK
clock => dffe5a[1].CLK
clock => dffe5a[0].CLK
clrn => dffe5a[7].ACLR
clrn => dffe5a[6].ACLR
clrn => dffe5a[5].ACLR
clrn => dffe5a[4].ACLR
clrn => dffe5a[3].ACLR
clrn => dffe5a[2].ACLR
clrn => dffe5a[1].ACLR
clrn => dffe5a[0].ACLR
q[0] <= dffe5a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffe5a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffe5a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffe5a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffe5a[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffe5a[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffe5a[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffe5a[7].DB_MAX_OUTPUT_PORT_TYPE


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp
clock => dffpipe_id9:dffpipe10.clock
clrn => dffpipe_id9:dffpipe10.clrn
d[0] => dffpipe_id9:dffpipe10.d[0]
d[1] => dffpipe_id9:dffpipe10.d[1]
d[2] => dffpipe_id9:dffpipe10.d[2]
d[3] => dffpipe_id9:dffpipe10.d[3]
d[4] => dffpipe_id9:dffpipe10.d[4]
d[5] => dffpipe_id9:dffpipe10.d[5]
d[6] => dffpipe_id9:dffpipe10.d[6]
d[7] => dffpipe_id9:dffpipe10.d[7]
q[0] <= dffpipe_id9:dffpipe10.q[0]
q[1] <= dffpipe_id9:dffpipe10.q[1]
q[2] <= dffpipe_id9:dffpipe10.q[2]
q[3] <= dffpipe_id9:dffpipe10.q[3]
q[4] <= dffpipe_id9:dffpipe10.q[4]
q[5] <= dffpipe_id9:dffpipe10.q[5]
q[6] <= dffpipe_id9:dffpipe10.q[6]
q[7] <= dffpipe_id9:dffpipe10.q[7]


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|alt_synch_pipe_oc8:dffpipe_ws_dgrp|dffpipe_id9:dffpipe10
clock => dffe11a[7].CLK
clock => dffe11a[6].CLK
clock => dffe11a[5].CLK
clock => dffe11a[4].CLK
clock => dffe11a[3].CLK
clock => dffe11a[2].CLK
clock => dffe11a[1].CLK
clock => dffe11a[0].CLK
clock => dffe12a[7].CLK
clock => dffe12a[6].CLK
clock => dffe12a[5].CLK
clock => dffe12a[4].CLK
clock => dffe12a[3].CLK
clock => dffe12a[2].CLK
clock => dffe12a[1].CLK
clock => dffe12a[0].CLK
clock => dffe13a[7].CLK
clock => dffe13a[6].CLK
clock => dffe13a[5].CLK
clock => dffe13a[4].CLK
clock => dffe13a[3].CLK
clock => dffe13a[2].CLK
clock => dffe13a[1].CLK
clock => dffe13a[0].CLK
clrn => dffe11a[7].ACLR
clrn => dffe11a[6].ACLR
clrn => dffe11a[5].ACLR
clrn => dffe11a[4].ACLR
clrn => dffe11a[3].ACLR
clrn => dffe11a[2].ACLR
clrn => dffe11a[1].ACLR
clrn => dffe11a[0].ACLR
clrn => dffe12a[7].ACLR
clrn => dffe12a[6].ACLR
clrn => dffe12a[5].ACLR
clrn => dffe12a[4].ACLR
clrn => dffe12a[3].ACLR
clrn => dffe12a[2].ACLR
clrn => dffe12a[1].ACLR
clrn => dffe12a[0].ACLR
clrn => dffe13a[7].ACLR
clrn => dffe13a[6].ACLR
clrn => dffe13a[5].ACLR
clrn => dffe13a[4].ACLR
clrn => dffe13a[3].ACLR
clrn => dffe13a[2].ACLR
clrn => dffe13a[1].ACLR
clrn => dffe13a[0].ACLR
q[0] <= dffe13a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffe13a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffe13a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffe13a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffe13a[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffe13a[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffe13a[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffe13a[7].DB_MAX_OUTPUT_PORT_TYPE


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dffpipe_fd9:dffpipe_ws_nbrp
clock => dffe5a[7].CLK
clock => dffe5a[6].CLK
clock => dffe5a[5].CLK
clock => dffe5a[4].CLK
clock => dffe5a[3].CLK
clock => dffe5a[2].CLK
clock => dffe5a[1].CLK
clock => dffe5a[0].CLK
clrn => dffe5a[7].ACLR
clrn => dffe5a[6].ACLR
clrn => dffe5a[5].ACLR
clrn => dffe5a[4].ACLR
clrn => dffe5a[3].ACLR
clrn => dffe5a[2].ACLR
clrn => dffe5a[1].ACLR
clrn => dffe5a[0].ACLR
q[0] <= dffe5a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffe5a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffe5a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffe5a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffe5a[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffe5a[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffe5a[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffe5a[7].DB_MAX_OUTPUT_PORT_TYPE


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|add_sub_fub:lpm_add_sub_rd_udwn
datab[0] => datab_node[0].IN0
datab[1] => datab_node[1].IN0
datab[2] => datab_node[2].IN0
datab[3] => datab_node[3].IN0
datab[4] => datab_node[4].IN0
datab[5] => datab_node[5].IN0
datab[6] => datab_node[6].IN0
datab[7] => datab_node[7].IN0