fifo.hier_info

用VERILOG写的FIFO程序

|fifo
clk => clk~0.IN3
rst_n => rst_n~0.IN2
CH451_DCLK <= DISPLAY:M4.CH451_DCLK
CH451_DIN <= DISPLAY:M4.CH451_DIN
CH451_LOAD <= DISPLAY:M4.CH451_LOAD


|fifo|fifo_ram:M1
data[0] => data[0]~7.IN1
data[1] => data[1]~6.IN1
data[2] => data[2]~5.IN1
data[3] => data[3]~4.IN1
data[4] => data[4]~3.IN1
data[5] => data[5]~2.IN1
data[6] => data[6]~1.IN1
data[7] => data[7]~0.IN1
rdclk => rdclk~0.IN1
rdreq => rdreq~0.IN1
wrclk => wrclk~0.IN1
wrreq => wrreq~0.IN1
q[0] <= dcfifo:dcfifo_component.q
q[1] <= dcfifo:dcfifo_component.q
q[2] <= dcfifo:dcfifo_component.q
q[3] <= dcfifo:dcfifo_component.q
q[4] <= dcfifo:dcfifo_component.q
q[5] <= dcfifo:dcfifo_component.q
q[6] <= dcfifo:dcfifo_component.q
q[7] <= dcfifo:dcfifo_component.q
rdempty <= dcfifo:dcfifo_component.rdempty
wrfull <= dcfifo:dcfifo_component.wrfull


|fifo|fifo_ram:M1|dcfifo:dcfifo_component
data[0] => dcfifo_et91:auto_generated.data[0]
data[1] => dcfifo_et91:auto_generated.data[1]
data[2] => dcfifo_et91:auto_generated.data[2]
data[3] => dcfifo_et91:auto_generated.data[3]
data[4] => dcfifo_et91:auto_generated.data[4]
data[5] => dcfifo_et91:auto_generated.data[5]
data[6] => dcfifo_et91:auto_generated.data[6]
data[7] => dcfifo_et91:auto_generated.data[7]
q[0] <= dcfifo_et91:auto_generated.q[0]
q[1] <= dcfifo_et91:auto_generated.q[1]
q[2] <= dcfifo_et91:auto_generated.q[2]
q[3] <= dcfifo_et91:auto_generated.q[3]
q[4] <= dcfifo_et91:auto_generated.q[4]
q[5] <= dcfifo_et91:auto_generated.q[5]
q[6] <= dcfifo_et91:auto_generated.q[6]
q[7] <= dcfifo_et91:auto_generated.q[7]
rdclk => dcfifo_et91:auto_generated.rdclk
rdreq => dcfifo_et91:auto_generated.rdreq
wrclk => dcfifo_et91:auto_generated.wrclk
wrreq => dcfifo_et91:auto_generated.wrreq
aclr => ~NO_FANOUT~
rdempty <= dcfifo_et91:auto_generated.rdempty
rdfull <= <UNC>
wrempty <= <GND>
wrfull <= dcfifo_et91:auto_generated.wrfull
rdusedw[0] <= <UNC>
rdusedw[1] <= <UNC>
rdusedw[2] <= <UNC>
rdusedw[3] <= <UNC>
rdusedw[4] <= <UNC>
rdusedw[5] <= <UNC>
rdusedw[6] <= <UNC>
rdusedw[7] <= <UNC>
wrusedw[0] <= <GND>
wrusedw[1] <= <GND>
wrusedw[2] <= <GND>
wrusedw[3] <= <GND>
wrusedw[4] <= <GND>
wrusedw[5] <= <GND>
wrusedw[6] <= <GND>
wrusedw[7] <= <GND>


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated
data[0] => dpram_5ur:fiforam.data[0]
data[1] => dpram_5ur:fiforam.data[1]
data[2] => dpram_5ur:fiforam.data[2]
data[3] => dpram_5ur:fiforam.data[3]
data[4] => dpram_5ur:fiforam.data[4]
data[5] => dpram_5ur:fiforam.data[5]
data[6] => dpram_5ur:fiforam.data[6]
data[7] => dpram_5ur:fiforam.data[7]
q[0] <= dpram_5ur:fiforam.q[0]
q[1] <= dpram_5ur:fiforam.q[1]
q[2] <= dpram_5ur:fiforam.q[2]
q[3] <= dpram_5ur:fiforam.q[3]
q[4] <= dpram_5ur:fiforam.q[4]
q[5] <= dpram_5ur:fiforam.q[5]
q[6] <= dpram_5ur:fiforam.q[6]
q[7] <= dpram_5ur:fiforam.q[7]
rdclk => a_fefifo_gtc:read_state.clock
rdclk => a_graycounter_t06:rdptr_g.clock
rdclk => dpram_5ur:fiforam.outclock
rdclk => dffpipe_fd9:dffpipe_rdbuw.clock
rdclk => dffpipe_fd9:dffpipe_rdusedw.clock
rdclk => dffpipe_fd9:dffpipe_rs_dbwp.clock
rdclk => alt_synch_pipe_nc8:dffpipe_rs_dgwp.clock
rdclk => cntr_9v7:rdptr_b.clock
rdempty <= a_fefifo_gtc:read_state.empty
rdfull <= a_fefifo_gtc:read_state.full
rdreq => a_fefifo_gtc:read_state.rreq
rdreq => valid_rreq.IN0
rdusedw[0] <= dffpipe_fd9:dffpipe_rdusedw.q[0]
rdusedw[1] <= dffpipe_fd9:dffpipe_rdusedw.q[1]
rdusedw[2] <= dffpipe_fd9:dffpipe_rdusedw.q[2]
rdusedw[3] <= dffpipe_fd9:dffpipe_rdusedw.q[3]
rdusedw[4] <= dffpipe_fd9:dffpipe_rdusedw.q[4]
rdusedw[5] <= dffpipe_fd9:dffpipe_rdusedw.q[5]
rdusedw[6] <= dffpipe_fd9:dffpipe_rdusedw.q[6]
rdusedw[7] <= dffpipe_fd9:dffpipe_rdusedw.q[7]
wrclk => a_fefifo_ltc:write_state.clock
wrclk => a_graycounter_t06:wrptr_g.clock
wrclk => dpram_5ur:fiforam.inclock
wrclk => dffpipe_fd9:dffpipe_wr_dbuw.clock
wrclk => dffpipe_fd9:dffpipe_wrusedw.clock
wrclk => alt_synch_pipe_oc8:dffpipe_ws_dgrp.clock
wrclk => dffpipe_fd9:dffpipe_ws_nbrp.clock
wrclk => cntr_9v7:wrptr_b.clock
wrclk => write_delay_cycle[7].CLK
wrclk => write_delay_cycle[6].CLK
wrclk => write_delay_cycle[5].CLK
wrclk => write_delay_cycle[4].CLK
wrclk => write_delay_cycle[3].CLK
wrclk => write_delay_cycle[2].CLK
wrclk => write_delay_cycle[1].CLK
wrclk => write_delay_cycle[0].CLK
wrempty <= a_fefifo_ltc:write_state.empty
wrfull <= a_fefifo_ltc:write_state.full
wrreq => a_fefifo_ltc:write_state.wreq
wrreq => valid_wreq.IN0
wrusedw[0] <= dffpipe_fd9:dffpipe_wrusedw.q[0]
wrusedw[1] <= dffpipe_fd9:dffpipe_wrusedw.q[1]
wrusedw[2] <= dffpipe_fd9:dffpipe_wrusedw.q[2]
wrusedw[3] <= dffpipe_fd9:dffpipe_wrusedw.q[3]
wrusedw[4] <= dffpipe_fd9:dffpipe_wrusedw.q[4]
wrusedw[5] <= dffpipe_fd9:dffpipe_wrusedw.q[5]
wrusedw[6] <= dffpipe_fd9:dffpipe_wrusedw.q[6]
wrusedw[7] <= dffpipe_fd9:dffpipe_wrusedw.q[7]


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|a_fefifo_gtc:read_state
clock => b_full.CLK
clock => b_non_empty.CLK
clock => b_one.CLK
clock => llreq.CLK
full <= b_full.DB_MAX_OUTPUT_PORT_TYPE
usedw_in[0] => is_one0.IN0
usedw_in[0] => is_two0.IN0
usedw_in[0] => is_zero0.IN0
usedw_in[0] => op_1.IN16
usedw_in[1] => op_1.IN14
usedw_in[2] => op_1.IN12
usedw_in[3] => op_1.IN10
usedw_in[4] => op_1.IN8
usedw_in[5] => op_1.IN6
usedw_in[6] => op_1.IN4
usedw_in[7] => op_1.IN2


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|a_fefifo_ltc:write_state
clock => b_full.CLK
clock => b_non_empty.CLK
clock => b_one.CLK
full <= b_full.DB_MAX_OUTPUT_PORT_TYPE
usedw_in[0] => is_zero0.IN0
usedw_in[0] => op_1.IN16
usedw_in[1] => op_1.IN14
usedw_in[2] => op_1.IN12
usedw_in[3] => op_1.IN10
usedw_in[4] => op_1.IN8
usedw_in[5] => op_1.IN6
usedw_in[6] => op_1.IN4
usedw_in[7] => op_1.IN2


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|a_gray2bin_p4b:gray2bin_rs_nbwp
bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
bin[7] <= gray[7].DB_MAX_OUTPUT_PORT_TYPE
gray[0] => xor0.IN0
gray[1] => xor1.IN0
gray[2] => xor2.IN0
gray[3] => xor3.IN0
gray[4] => xor4.IN0
gray[5] => xor5.IN0
gray[6] => xor6.IN1
gray[7] => bin[7].DATAIN
gray[7] => xor6.IN0


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|a_gray2bin_p4b:gray2bin_ws_nbrp
bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
bin[7] <= gray[7].DB_MAX_OUTPUT_PORT_TYPE
gray[0] => xor0.IN0
gray[1] => xor1.IN0
gray[2] => xor2.IN0
gray[3] => xor3.IN0
gray[4] => xor4.IN0
gray[5] => xor5.IN0
gray[6] => xor6.IN1
gray[7] => bin[7].DATAIN
gray[7] => xor6.IN0


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|a_graycounter_t06:rdptr_g
aclr => countera0.ACLR
aclr => countera1.ACLR
aclr => countera2.ACLR
aclr => countera3.ACLR
aclr => countera4.ACLR
aclr => countera5.ACLR
aclr => countera6.ACLR
aclr => countera7.ACLR
aclr => parity.ACLR
clock => countera0.CLK
clock => countera1.CLK
clock => countera2.CLK
clock => countera3.CLK
clock => countera4.CLK
clock => countera5.CLK
clock => countera6.CLK
clock => countera7.CLK
clock => parity.CLK
cnt_en => countera0.DATAA
cnt_en => parity.DATAA
q[0] <= countera0.REGOUT
q[1] <= countera1.REGOUT
q[2] <= countera2.REGOUT
q[3] <= countera3.REGOUT
q[4] <= countera4.REGOUT
q[5] <= countera5.REGOUT
q[6] <= countera6.REGOUT
q[7] <= countera7.REGOUT


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|a_graycounter_t06:wrptr_g
aclr => countera0.ACLR
aclr => countera1.ACLR
aclr => countera2.ACLR
aclr => countera3.ACLR
aclr => countera4.ACLR
aclr => countera5.ACLR
aclr => countera6.ACLR
aclr => countera7.ACLR
aclr => parity.ACLR
clock => countera0.CLK
clock => countera1.CLK
clock => countera2.CLK
clock => countera3.CLK
clock => countera4.CLK
clock => countera5.CLK
clock => countera6.CLK
clock => countera7.CLK
clock => parity.CLK
cnt_en => countera0.DATAA
cnt_en => parity.DATAA
q[0] <= countera0.REGOUT
q[1] <= countera1.REGOUT
q[2] <= countera2.REGOUT
q[3] <= countera3.REGOUT
q[4] <= countera4.REGOUT
q[5] <= countera5.REGOUT
q[6] <= countera6.REGOUT
q[7] <= countera7.REGOUT


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam
data[0] => altsyncram_7mf1:altsyncram3.data_a[0]
data[1] => altsyncram_7mf1:altsyncram3.data_a[1]
data[2] => altsyncram_7mf1:altsyncram3.data_a[2]
data[3] => altsyncram_7mf1:altsyncram3.data_a[3]
data[4] => altsyncram_7mf1:altsyncram3.data_a[4]
data[5] => altsyncram_7mf1:altsyncram3.data_a[5]
data[6] => altsyncram_7mf1:altsyncram3.data_a[6]
data[7] => altsyncram_7mf1:altsyncram3.data_a[7]
inclock => altsyncram_7mf1:altsyncram3.clock0
outclock => altsyncram_7mf1:altsyncram3.clock1
outclocken => altsyncram_7mf1:altsyncram3.clocken1
q[0] <= altsyncram_7mf1:altsyncram3.q_b[0]
q[1] <= altsyncram_7mf1:altsyncram3.q_b[1]
q[2] <= altsyncram_7mf1:altsyncram3.q_b[2]
q[3] <= altsyncram_7mf1:altsyncram3.q_b[3]
q[4] <= altsyncram_7mf1:altsyncram3.q_b[4]
q[5] <= altsyncram_7mf1:altsyncram3.q_b[5]
q[6] <= altsyncram_7mf1:altsyncram3.q_b[6]
q[7] <= altsyncram_7mf1:altsyncram3.q_b[7]
rdaddress[0] => altsyncram_7mf1:altsyncram3.address_b[0]
rdaddress[1] => altsyncram_7mf1:altsyncram3.address_b[1]
rdaddress[2] => altsyncram_7mf1:altsyncram3.address_b[2]
rdaddress[3] => altsyncram_7mf1:altsyncram3.address_b[3]
rdaddress[4] => altsyncram_7mf1:altsyncram3.address_b[4]
rdaddress[5] => altsyncram_7mf1:altsyncram3.address_b[5]
rdaddress[6] => altsyncram_7mf1:altsyncram3.address_b[6]
rdaddress[7] => altsyncram_7mf1:altsyncram3.address_b[7]
wraddress[0] => altsyncram_7mf1:altsyncram3.address_a[0]
wraddress[1] => altsyncram_7mf1:altsyncram3.address_a[1]
wraddress[2] => altsyncram_7mf1:altsyncram3.address_a[2]
wraddress[3] => altsyncram_7mf1:altsyncram3.address_a[3]
wraddress[4] => altsyncram_7mf1:altsyncram3.address_a[4]
wraddress[5] => altsyncram_7mf1:altsyncram3.address_a[5]
wraddress[6] => altsyncram_7mf1:altsyncram3.address_a[6]
wraddress[7] => altsyncram_7mf1:altsyncram3.address_a[7]
wren => altsyncram_7mf1:altsyncram3.wren_a


|fifo|fifo_ram:M1|dcfifo:dcfifo_component|dcfifo_et91:auto_generated|dpram_5ur:fiforam|altsyncram_7mf1:altsyncram3
address_a[0] => ram_block4a0.PORTAADDR
address_a[0] => ram_block4a1.PORTAADDR
address_a[0] => ram_block4a2.PORTAADDR
address_a[0] => ram_block4a3.PORTAADDR
address_a[0] => ram_block4a4.PORTAADDR
address_a[0] => ram_block4a5.PORTAADDR
address_a[0] => ram_block4a6.PORTAADDR
address_a[0] => ram_block4a7.PORTAADDR
address_a[1] => ram_block4a0.PORTAADDR1
address_a[1] => ram_block4a1.PORTAADDR1
address_a[1] => ram_block4a2.PORTAADDR1
address_a[1] => ram_block4a3.PORTAADDR1
address_a[1] => ram_block4a4.PORTAADDR1
address_a[1] => ram_block4a5.PORTAADDR1
address_a[1] => ram_block4a6.PORTAADDR1
address_a[1] => ram_block4a7.PORTAADDR1
address_a[2] => ram_block4a0.PORTAADDR2
address_a[2] => ram_block4a1.PORTAADDR2
address_a[2] => ram_block4a2.PORTAADDR2
address_a[2] => ram_block4a3.PORTAADDR2
address_a[2] => ram_block4a4.PORTAADDR2
address_a[2] => ram_block4a5.PORTAADDR2
address_a[2] => ram_block4a6.PORTAADDR2
address_a[2] => ram_block4a7.PORTAADDR2
address_a[3] => ram_block4a0.PORTAADDR3
address_a[3] => ram_block4a1.PORTAADDR3
address_a[3] => ram_block4a2.PORTAADDR3
address_a[3] => ram_block4a3.PORTAADDR3
address_a[3] => ram_block4a4.PORTAADDR3
address_a[3] => ram_block4a5.PORTAADDR3
address_a[3] => ram_block4a6.PORTAADDR3
address_a[3] => ram_block4a7.PORTAADDR3
address_a[4] => ram_block4a0.PORTAADDR4
address_a[4] => ram_block4a1.PORTAADDR4
address_a[4] => ram_block4a2.PORTAADDR4
address_a[4] => ram_block4a3.PORTAADDR4
address_a[4] => ram_block4a4.PORTAADDR4
address_a[4] => ram_block4a5.PORTAADDR4
address_a[4] => ram_block4a6.PORTAADDR4
address_a[4] => ram_block4a7.PORTAADDR4
address_a[5] => ram_block4a0.PORTAADDR5
address_a[5] => ram_block4a1.PORTAADDR5
address_a[5] => ram_block4a2.PORTAADDR5
address_a[5] => ram_block4a3.PORTAADDR5
address_a[5] => ram_block4a4.PORTAADDR5
address_a[5] => ram_block4a5.PORTAADDR5
address_a[5] => ram_block4a6.PORTAADDR5
address_a[5] => ram_block4a7.PORTAADDR5
address_a[6] => ram_block4a0.PORTAADDR6
address_a[6] => ram_block4a1.PORTAADDR6
address_a[6] => ram_block4a2.PORTAADDR6
address_a[6] => ram_block4a3.PORTAADDR6
address_a[6] => ram_block4a4.PORTAADDR6
address_a[6] => ram_block4a5.PORTAADDR6
address_a[6] => ram_block4a6.PORTAADDR6
address_a[6] => ram_block4a7.PORTAADDR6
address_a[7] => ram_block4a0.PORTAADDR7
address_a[7] => ram_block4a1.PORTAADDR7
address_a[7] => ram_block4a2.PORTAADDR7
address_a[7] => ram_block4a3.PORTAADDR7
address_a[7] => ram_block4a4.PORTAADDR7
address_a[7] => ram_block4a5.PORTAADDR7
address_a[7] => ram_block4a6.PORTAADDR7
address_a[7] => ram_block4a7.PORTAADDR7
address_b[0] => ram_block4a0.PORTBADDR
address_b[0] => ram_block4a1.PORTBADDR
address_b[0] => ram_block4a2.PORTBADDR
address_b[0] => ram_block4a3.PORTBADDR
address_b[0] => ram_block4a4.PORTBADDR
address_b[0] => ram_block4a5.PORTBADDR
address_b[0] => ram_block4a6.PORTBADDR
address_b[0] => ram_block4a7.PORTBADDR
address_b[1] => ram_block4a0.PORTBADDR1
address_b[1] => ram_block4a1.PORTBADDR1
address_b[1] => ram_block4a2.PORTBADDR1
address_b[1] => ram_block4a3.PORTBADDR1
address_b[1] => ram_block4a4.PORTBADDR1
address_b[1] => ram_block4a5.PORTBADDR1
address_b[1] => ram_block4a6.PORTBADDR1
address_b[1] => ram_block4a7.PORTBADDR1
address_b[2] => ram_block4a0.PORTBADDR2
address_b[2] => ram_block4a1.PORTBADDR2
address_b[2] => ram_block4a2.PORTBADDR2
address_b[2] => ram_block4a3.PORTBADDR2
address_b[2] => ram_block4a4.PORTBADDR2
address_b[2] => ram_block4a5.PORTBADDR2
address_b[2] => ram_block4a6.PORTBADDR2
address_b[2] => ram_block4a7.PORTBADDR2
address_b[3] => ram_block4a0.PORTBADDR3
address_b[3] => ram_block4a1.PORTBADDR3
address_b[3] => ram_block4a2.PORTBADDR3
address_b[3] => ram_block4a3.PORTBADDR3
address_b[3] => ram_block4a4.PORTBADDR3
address_b[3] => ram_block4a5.PORTBADDR3