fifo.fit.qmsg

用VERILOG写的FIFO程序

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.594 ns register register " "Info: Estimated most critical path is register to register delay of 1.594 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rd_data\[1\] 1 REG LAB_X22_Y11 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X22_Y11; Fanout = 1; REG Node = 'rd_data\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rd_data[1] } "NODE_NAME" } } { "fifo.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo.v" 124 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.987 ns) + CELL(0.607 ns) 1.594 ns DISPLAY:M4\|display_data\[1\] 2 REG LAB_X22_Y13 2 " "Info: 2: + IC(0.987 ns) + CELL(0.607 ns) = 1.594 ns; Loc. = LAB_X22_Y13; Fanout = 2; REG Node = 'DISPLAY:M4\|display_data\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.594 ns" { rd_data[1] DISPLAY:M4|display_data[1] } "NODE_NAME" } } { "DISPLAY.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/DISPLAY.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.607 ns ( 38.08 % ) " "Info: Total cell delay = 0.607 ns ( 38.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.987 ns ( 61.92 % ) " "Info: Total interconnect delay = 0.987 ns ( 61.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.594 ns" { rd_data[1] DISPLAY:M4|display_data[1] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 4 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 4%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x12_y11 x23_y21 " "Info: The peak interconnect region extends from location x12_y11 to location x23_y21" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "rst_n " "Info: Node rst_n uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear DISPLAY:M4\|display_data\[31\] " "Info: Port clear -- assigned as a global for destination node DISPLAY:M4\|display_data\[31\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DISPLAY:M4|display_data[31] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DISPLAY:M4\|display_data\[31\]" } } } } { "DISPLAY.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/DISPLAY.v" 88 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DISPLAY:M4|display_data[31] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear DISPLAY:M4\|display_led_sel\[3\] " "Info: Port clear -- assigned as a global for destination node DISPLAY:M4\|display_led_sel\[3\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DISPLAY:M4|display_led_sel[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DISPLAY:M4\|display_led_sel\[3\]" } } } } { "DISPLAY.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/DISPLAY.v" 88 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DISPLAY:M4|display_led_sel[3] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear DISPLAY:M4\|display_data\[7\] " "Info: Port clear -- assigned as a global for destination node DISPLAY:M4\|display_data\[7\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DISPLAY:M4|display_data[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DISPLAY:M4\|display_data\[7\]" } } } } { "DISPLAY.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/DISPLAY.v" 88 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DISPLAY:M4|display_data[7] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear DISPLAY:M4\|display_led_sel\[4\] " "Info: Port clear -- assigned as a global for destination node DISPLAY:M4\|display_led_sel\[4\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DISPLAY:M4|display_led_sel[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DISPLAY:M4\|display_led_sel\[4\]" } } } } { "DISPLAY.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/DISPLAY.v" 88 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DISPLAY:M4|display_led_sel[4] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear DISPLAY:M4\|display_data\[29\] " "Info: Port clear -- assigned as a global for destination node DISPLAY:M4\|display_data\[29\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DISPLAY:M4|display_data[29] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DISPLAY:M4\|display_data\[29\]" } } } } { "DISPLAY.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/DISPLAY.v" 88 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DISPLAY:M4|display_data[29] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear DISPLAY:M4\|display_data\[25\] " "Info: Port clear -- assigned as a global for destination node DISPLAY:M4\|display_data\[25\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DISPLAY:M4|display_data[25] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DISPLAY:M4\|display_data\[25\]" } } } } { "DISPLAY.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/DISPLAY.v" 88 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DISPLAY:M4|display_data[25] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear DISPLAY:M4\|display_data\[27\] " "Info: Port clear -- assigned as a global for destination node DISPLAY:M4\|display_data\[27\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DISPLAY:M4|display_data[27] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DISPLAY:M4\|display_data\[27\]" } } } } { "DISPLAY.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/DISPLAY.v" 88 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DISPLAY:M4|display_data[27] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear DISPLAY:M4\|display_data\[3\] " "Info: Port clear -- assigned as a global for destination node DISPLAY:M4\|display_data\[3\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DISPLAY:M4|display_data[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DISPLAY:M4\|display_data\[3\]" } } } } { "DISPLAY.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/DISPLAY.v" 88 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DISPLAY:M4|display_data[3] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst_n } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "fifo.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo.v" 10 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst_n } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "system_rst:M2\|system_rst " "Info: Node system_rst:M2\|system_rst uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rd_data\[2\] " "Info: Port clear -- assigned as a global for destination node rd_data\[2\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rd_data[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "rd_data\[2\]" } } } } { "fifo.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo.v" 124 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rd_data[2] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rd_data\[5\] " "Info: Port clear -- assigned as a global for destination node rd_data\[5\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rd_data[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "rd_data\[5\]" } } } } { "fifo.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo.v" 124 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rd_data[5] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rd_data\[6\] " "Info: Port clear -- assigned as a global for destination node rd_data\[6\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rd_data[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "rd_data\[6\]" } } } } { "fifo.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo.v" 124 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rd_data[6] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rd_data\[4\] " "Info: Port clear -- assigned as a global for destination node rd_data\[4\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rd_data[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "rd_data\[4\]" } } } } { "fifo.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo.v" 124 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rd_data[4] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rd_data\[0\] " "Info: Port clear -- assigned as a global for destination node rd_data\[0\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rd_data[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "rd_data\[0\]" } } } } { "fifo.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo.v" 124 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rd_data[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_rst:M2|system_rst } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_rst:M2\|system_rst" } } } } { "system_rst.v" "" { Text "C:/Documents and Settings/Jaylee/桌面/fifo_test/system_rst.v" 9 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_rst:M2|system_rst } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun May 18 15:54:48 2008 " "Info: Processing ended: Sun May 18 15:54:48 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo.fit.smsg " "Info: Generated suppressed messages file C:/Documents and Settings/Jaylee/桌面/fifo_test/fifo.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}