mul.vhd

VHDL乘法器 四输入 四输出的代码设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
package pack is
	function mult(a,b:unsigned) return unsigned;
end pack;

package body pack is
	function mult(a,b:unsigned) return unsigned is
		constant max: integer:=a'length+b'length-1;
		variable aa:unsigned(max downto 0) :=(max downto a'length=>'0')&a(a'length-1 downto 0);
		variable prod: unsigned(max downto 0) := (others =>'0');
	begin
		for i in 0 to a'length-1 loop
			if(b(i) ='1') then prod:=prod +aa;
			end if;
			aa:=aa(max-1 downto 0)&'0';
		end loop;
		return prod;
	end mult;
end pack;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.pack.all;

entity Mul is
	generic (size : integer :=4);
	port(a,b: in unsigned(size-1 downto 0);
		y: out unsigned(2*size-1 downto 0));
end Mul;

architecture behave of Mul is
	begin
		y<=mult(a,b);
end behave;