mul.map.qmsg

VHDL乘法器 四输入 四输出的代码设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 17 13:04:34 2008 " "Info: Processing started: Wed Dec 17 13:04:34 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off Mul -c Mul " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Mul -c Mul" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Mul.vhd 4 1 " "Info: Found 4 design units, including 1 entities, in source file Mul.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pack " "Info: Found design unit 1: pack" {  } { { "d:/选做实验2/mul/Mul.vhd" "pack" "" { Text "d:/选做实验2/mul/Mul.vhd" 4 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 pack-body " "Info: Found design unit 2: pack-body" {  } { { "d:/选做实验2/mul/Mul.vhd" "pack-body" "" { Text "d:/选做实验2/mul/Mul.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 Mul-behave " "Info: Found design unit 3: Mul-behave" {  } { { "d:/选做实验2/mul/Mul.vhd" "Mul-behave" "" { Text "d:/选做实验2/mul/Mul.vhd" 34 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 Mul " "Info: Found entity 1: Mul" {  } { { "d:/选做实验2/mul/Mul.vhd" "Mul" "" { Text "d:/选做实验2/mul/Mul.vhd" 28 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "50 " "Info: Implemented 50 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "8 " "Info: Implemented 8 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "34 " "Info: Implemented 34 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 17 13:04:35 2008 " "Info: Processing ended: Wed Dec 17 13:04:35 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}