📄 mul.fit.rpt
字号:
Fitter report for Mul
Wed Dec 17 13:04:38 2008
Version 4.1 Build 181 06/29/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Device Options
5. Fitter Equations
6. Floorplan View
7. Pin-Out File
8. Fitter Resource Usage Summary
9. Input Pins
10. Output Pins
11. I/O Bank Usage
12. All Package Pins
13. Output Pin Load For Reported TCO
14. Fitter Resource Utilization by Entity
15. Delay Chain Summary
16. Pad To Core Delay Chain Fanout
17. Non-Global High Fan-Out Signals
18. Interconnect Usage Summary
19. LAB Logic Elements
20. LAB Signals Sourced
21. LAB Signals Sourced Out
22. LAB Distinct Inputs
23. Fitter Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+------------------------------------------+
; Fitter Status ; Successful - Wed Dec 17 13:04:38 2008 ;
; Quartus II Version ; 4.1 Build 181 06/29/2004 SJ Full Version ;
; Revision Name ; Mul ;
; Top-level Entity Name ; Mul ;
; Family ; Cyclone ;
; Device ; EP1C3T144C8 ;
; Timing Models ; Production ;
; Total logic elements ; 34 / 2,910 ( 1 % ) ;
; Total pins ; 16 / 104 ( 15 % ) ;
; Total memory bits ; 0 / 59,904 ( 0 % ) ;
; Total PLLs ; 0 / 1 ( 0 % ) ;
+-----------------------+------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EP1C3T144C8 ; ;
; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Slow Slew Rate ; Off ; Off ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Auto Packed Registers -- Cyclone ; Auto ; Auto ;
; Auto Delay Chains ; On ; On ;
; Auto Merge PLLs ; On ; On ;
; Perform Physical Synthesis for Combinational Logic ; Off ; Off ;
; Perform Register Duplication ; Off ; Off ;
; Perform Register Retiming ; Off ; Off ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Logic Cell Insertion -- Logic Duplication ; Auto ; Auto ;
; Auto Register Duplication ; Off ; Off ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
+----------------------------------------------------+--------------------------------+--------------------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Auto-restart configuration after error ; On ;
; Release clears before tri-states ; Off ;
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Active Serial ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in d:/选做实验2/mul/Mul.fit.eqn.
+----------------+
; Floorplan View ;
+----------------+
Floorplan report data cannot be output to ASCII.
Please use Quartus II to view the floorplan report data.
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in d:/选做实验2/mul/Mul.pin.
+-----------------------------------------------------+
; Fitter Resource Usage Summary ;
+--------------------------------+--------------------+
; Resource ; Usage ;
+--------------------------------+--------------------+
; Logic cells ; 34 / 2,910 ( 1 % ) ;
; Registers ; 0 / 3,210 ( 0 % ) ;
; Total LABs ; 5 / 291 ( 1 % ) ;
; Logic elements in carry chains ; 15 ;
; User inserted logic cells ; 0 ;
; Virtual pins ; 0 ;
; I/O pins ; 16 / 104 ( 15 % ) ;
; -- Clock pins ; 0 / 2 ( 0 % ) ;
; Global signals ; 0 ;
; M4Ks ; 0 / 13 ( 0 % ) ;
; Total memory bits ; 0 / 59,904 ( 0 % ) ;
; Total RAM block bits ; 0 / 59,904 ( 0 % ) ;
; Global clocks ; 0 / 8 ( 0 % ) ;
; Maximum fan-out node ; b[1] ;
; Maximum fan-out ; 7 ;
; Total fan-out ; 98 ;
; Average fan-out ; 1.88 ;
+--------------------------------+--------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; a[0] ; 107 ; 3 ; 27 ; 13 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; Off ; LVTTL ; Off ; Fitter ;
; a[1] ; 109 ; 2 ; 26 ; 14 ; 0 ; 5 ; 0 ; no ; no ; no ; no ; no ; Off ; LVTTL ; Off ; Fitter ;
; a[2] ; 111 ; 2 ; 24 ; 14 ; 0 ; 5 ; 0 ; no ; no ; no ; no ; no ; Off ; LVTTL ; Off ; Fitter ;
; a[3] ; 110 ; 2 ; 26 ; 14 ; 1 ; 5 ; 0 ; no ; no ; no ; no ; no ; Off ; LVTTL ; Off ; Fitter ;
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