mul.map.summary

VHDL乘法器 四输入 四输出的代码设计

Flow Status : Successful - Wed Dec 17 13:04:35 2008
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : Mul
Top-level Entity Name : Mul
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Production
Total logic elements : 34
Total pins : 16
Total memory bits : 0
Total PLLs : 0