mark.vhd

来自「四路抢答器」· VHDL 代码 · 共 65 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mark is
   port(clk,up,dn:in std_logic;--加减分数
        table:in std_logic_vector(3 downto 0);--台号
        a1,a2,a3,a4:buffer std_logic_vector(3 downto 0));--得分
end mark;
architecture one of mark is
 begin
   process(clk,table,a1,a2,a3,a4,up,dn)--加减分数
   begin
    if clk'event and clk='1' then
                if table="0001" then 
                   if up='1' then
            if a1="1111" then
                 a1<="0000";
            else  a1<=a1+1;
            end if;
                    elsif dn='1' then 
             if a1="0000" then
                 a1<="0000";
            else  a1<=a1-1;
              end if;
					end if;
          elsif table="0010" then
                    if up='1' then
            if a1="1111" then
                 a2<="0000";
            else  a2<=a2+1;
            end if;
                    elsif dn='1' then 
             if a2="0000" then
                 a2<="0000";
            else  a2<=a2-1;
              end if;
					end if;
          elsif table="0011" then
            if up='1' then
            if a3="1111" then
                 a3<="0000";
            else  a3<=a3+1;
            end if;
                    elsif dn='1' then 
             if a3="0000" then
                 a3<="0000";
            else  a3<=a3-1;
              end if;
					end if;
          elsif table="0100" then
            if up='1' then
            if a4="1111" then
                 a4<="0000";
            else  a4<=a4+1;
            end if;
                    elsif dn='1' then 
             if a4="0000" then
                 a4<="0000";
            else  a4<=a4-1;
              end if;
					end if;
            end if;
          end if;
 end process;
end one;