stay.vhd

来自「四路抢答器」· VHDL 代码 · 共 55 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity stay is
  port(clk,en,rst:in std_logic;
       warn:out std_logic;--提前抢答警告
       back:buffer std_logic;--反馈
       k1,k2,k3,k4:in std_logic;
       table:out std_logic_vector(3 downto 0));--台号
end stay;
architecture one of stay  is

signal foul:std_logic;-- 警告
signal cnt:std_logic_vector(2 downto 0);--计数
begin

p1:process(k1,rst,k2,k3,k4,back)--抢答确认
  begin
    if rst='1'  then 
        back<='1';table<="0000";

      elsif back='1'  then
         if k1='1' then
       table<="0001";back<='0';
        
        elsif k2='1' then
        table<="0010";back<='0';
      
        elsif k3='1' then
        table<="0011";back<='0';
      
        elsif k4='1' then
        table<="0100";back<='0';
        
      else back<='1';table<="0000";
          end if ;
end if;
 end process p1;

p3:process(clk,en,back,rst,cnt)--提前抢答警告
   begin
   if rst='1' then
     cnt<="000";foul<='0';
   elsif clk'event and clk='1' then
    if en='0' and back='0' then
      if cnt<"111" then
        foul<=not foul;cnt<=cnt+1;--计数警告取反
      else foul<='0';
   end if;
end if;
end if;
end process p3;
warn<=foul;

end one;