xsim_t_e_s_t___c_p_u.cpp

32 risc cpu的参考设计

static const char * HSimCopyRightNotice = "Copyright 2004-2005, Xilinx Inc. All rights reserved.";
#ifdef __MINGW32__
#include "xsimMinGW.h"
#else
#include "xsim.h"
#endif


static HSim__s6* IF0(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkM_t_e_s_t___c_p_u(const char*);
    HSim__s6 *blk = createworkM_t_e_s_t___c_p_u(label); 
    return blk;
}


static HSim__s6* IF1(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMprom(const char*);
    HSim__s6 *blk = createworkMprom(label); 
    return blk;
}


static HSim__s6* IF2(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMdram(const char*);
    HSim__s6 *blk = createworkMdram(label); 
    return blk;
}


static HSim__s6* IF3(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMwb__connect(const char*);
    HSim__s6 *blk = createworkMwb__connect(label); 
    return blk;
}


static HSim__s6* IF4(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMwb__arbiter(const char*);
    HSim__s6 *blk = createworkMwb__arbiter(label); 
    return blk;
}


static HSim__s6* IF5(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMsdram__wbbus(const char*);
    HSim__s6 *blk = createworkMsdram__wbbus(label); 
    return blk;
}


static HSim__s6* IF6(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMicache(const char*);
    HSim__s6 *blk = createworkMicache(label); 
    return blk;
}


static HSim__s6* IF7(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMflash__wbbus(const char*);
    HSim__s6 *blk = createworkMflash__wbbus(label); 
    return blk;
}


static HSim__s6* IF8(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMdcache(const char*);
    HSim__s6 *blk = createworkMdcache(label); 
    return blk;
}


static HSim__s6* IF9(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMaddr__decoder(const char*);
    HSim__s6 *blk = createworkMaddr__decoder(label); 
    return blk;
}


static HSim__s6* IF10(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMwrite__back(const char*);
    HSim__s6 *blk = createworkMwrite__back(label); 
    return blk;
}


static HSim__s6* IF11(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMregfile(const char*);
    HSim__s6 *blk = createworkMregfile(label); 
    return blk;
}


static HSim__s6* IF12(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMreg__mem(const char*);
    HSim__s6 *blk = createworkMreg__mem(label); 
    return blk;
}


static HSim__s6* IF13(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMreg__if(const char*);
    HSim__s6 *blk = createworkMreg__if(label); 
    return blk;
}


static HSim__s6* IF14(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMreg__id(const char*);
    HSim__s6 *blk = createworkMreg__id(label); 
    return blk;
}


static HSim__s6* IF15(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMreg__ex(const char*);
    HSim__s6 *blk = createworkMreg__ex(label); 
    return blk;
}


static HSim__s6* IF16(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMpc__gen(const char*);
    HSim__s6 *blk = createworkMpc__gen(label); 
    return blk;
}


static HSim__s6* IF17(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMmpu(const char*);
    HSim__s6 *blk = createworkMmpu(label); 
    return blk;
}


static HSim__s6* IF18(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMinterrupt(const char*);
    HSim__s6 *blk = createworkMinterrupt(label); 
    return blk;
}


static HSim__s6* IF19(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMforward(const char*);
    HSim__s6 *blk = createworkMforward(label); 
    return blk;
}


static HSim__s6* IF20(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMdecode(const char*);
    HSim__s6 *blk = createworkMdecode(label); 
    return blk;
}


static HSim__s6* IF21(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMdcache__top(const char*);
    HSim__s6 *blk = createworkMdcache__top(label); 
    return blk;
}


static HSim__s6* IF22(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMcntrl__rf(const char*);
    HSim__s6 *blk = createworkMcntrl__rf(label); 
    return blk;
}


static HSim__s6* IF23(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMalu(const char*);
    HSim__s6 *blk = createworkMalu(label); 
    return blk;
}


static HSim__s6* IF24(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMcpu(const char*);
    HSim__s6 *blk = createworkMcpu(label); 
    return blk;
}


static HSim__s6* IF25(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMglbl(const char*);
    HSim__s6 *blk = createworkMglbl(label); 
    return blk;
}

class _top : public HSim__s6 {
public:
    _top() : HSim__s6(false, "_top", "_top", 0, 0, HSim::VerilogModule) {}
    HSimConfigDecl * topModuleInstantiate() {
        HSimConfigDecl * cfgvh = 0;
        cfgvh = new HSimConfigDecl("default");
        (*cfgvh).registerFuseLibList("unisims_ver;xilinxcorelib_ver");

        (*cfgvh).addVlogModule("work","TEST_CPU", (HSimInstFactoryPtr)IF0);
        (*cfgvh).addVlogModule("work","prom", (HSimInstFactoryPtr)IF1);
        (*cfgvh).addVlogModule("work","dram", (HSimInstFactoryPtr)IF2);
        (*cfgvh).addVlogModule("work","wb_connect", (HSimInstFactoryPtr)IF3);
        (*cfgvh).addVlogModule("work","wb_arbiter", (HSimInstFactoryPtr)IF4);
        (*cfgvh).addVlogModule("work","sdram_wbbus", (HSimInstFactoryPtr)IF5);
        (*cfgvh).addVlogModule("work","icache", (HSimInstFactoryPtr)IF6);
        (*cfgvh).addVlogModule("work","flash_wbbus", (HSimInstFactoryPtr)IF7);
        (*cfgvh).addVlogModule("work","dcache", (HSimInstFactoryPtr)IF8);
        (*cfgvh).addVlogModule("work","addr_decoder", (HSimInstFactoryPtr)IF9);
        (*cfgvh).addVlogModule("work","write_back", (HSimInstFactoryPtr)IF10);
        (*cfgvh).addVlogModule("work","regfile", (HSimInstFactoryPtr)IF11);
        (*cfgvh).addVlogModule("work","reg_mem", (HSimInstFactoryPtr)IF12);
        (*cfgvh).addVlogModule("work","reg_if", (HSimInstFactoryPtr)IF13);
        (*cfgvh).addVlogModule("work","reg_id", (HSimInstFactoryPtr)IF14);
        (*cfgvh).addVlogModule("work","reg_ex", (HSimInstFactoryPtr)IF15);
        (*cfgvh).addVlogModule("work","pc_gen", (HSimInstFactoryPtr)IF16);
        (*cfgvh).addVlogModule("work","mpu", (HSimInstFactoryPtr)IF17);
        (*cfgvh).addVlogModule("work","interrupt", (HSimInstFactoryPtr)IF18);
        (*cfgvh).addVlogModule("work","forward", (HSimInstFactoryPtr)IF19);
        (*cfgvh).addVlogModule("work","decode", (HSimInstFactoryPtr)IF20);
        (*cfgvh).addVlogModule("work","dcache_top", (HSimInstFactoryPtr)IF21);
        (*cfgvh).addVlogModule("work","cntrl_rf", (HSimInstFactoryPtr)IF22);
        (*cfgvh).addVlogModule("work","alu", (HSimInstFactoryPtr)IF23);
        (*cfgvh).addVlogModule("work","cpu", (HSimInstFactoryPtr)IF24);
        (*cfgvh).addVlogModule("work","glbl", (HSimInstFactoryPtr)IF25);
        HSim__s5 * topvl = 0;
        extern HSim__s6 * createworkM_t_e_s_t___c_p_u(const char*);
        topvl = (HSim__s5*)createworkM_t_e_s_t___c_p_u("TEST_CPU");
        topvl->moduleInstantiate(cfgvh);
        addChild(topvl);
        extern HSim__s6 * createworkMglbl(const char*);
        topvl = (HSim__s5*)createworkMglbl("glbl");
        topvl->moduleInstantiate(cfgvh);
        addChild(topvl);
        return cfgvh;
}
};

main(int argc, char **argv) {
  HSimDesign::initDesign();
  globalKernel->getOptions(argc,argv);
  HSim__s6 * _top_i = 0;
  try {
    HSimConfigDecl *cfg;
 _top_i = new _top();
  cfg =  _top_i->topModuleInstantiate();
    return globalKernel->runTcl(cfg, _top_i, "_top", argc, argv);
  }
  catch (HSimError& msg){
    try {
      globalKernel->error(msg.ErrMsg);
      return 1;
    }
    catch(...) {}
      return 1;
  }
  catch (...){
    globalKernel->fatalError();
    return 1;
  }
}