hdpdeps.ref

32 risc cpu的参考设计

V3 67
FL E:/potato_core/POTATO_TEST/cpu_verilog/alu.v 2008/03/11.21:27:14 J.36
MO work/alu FL E:/potato_core/POTATO_TEST/cpu_verilog/alu.v
FL E:/potato_core/POTATO_TEST/cpu_verilog/cntrl_rf.v 2008/03/10.21:56:00 J.36
MO work/cntrl_rf FL E:/potato_core/POTATO_TEST/cpu_verilog/cntrl_rf.v
FL E:/potato_core/POTATO_TEST/cpu_verilog/cpu.v 2008/03/11.21:35:16 J.36
MO work/cpu FL E:/potato_core/POTATO_TEST/cpu_verilog/cpu.v MI alu MI cntrl_rf \
      MI dcache_top MI decode MI forward MI interrupt MI mpu MI pc_gen MI reg_ex \
      MI reg_id MI reg_if MI reg_mem MI regfile MI write_back
FL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v 2008/03/11.22:16:54 J.36
MO work/dcache_top FL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v \
      MI addr_decoder MI dcache MI flash_wbbus MI icache MI sdram_wbbus MI wb_arbiter \
      MI wb_connect
MO work/wb_connect \
      FL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v
MO work/wb_arbiter \
      FL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v
MO work/addr_decoder \
      FL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v
MO work/dcache \
      FL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v
MO work/icache \
      FL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v
MO work/sdram_wbbus \
      FL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v MI dram
MO work/flash_wbbus \
      FL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v MI prom
MO work/dram \
      FL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v
MO work/prom \
      FL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v
FL E:/potato_core/POTATO_TEST/cpu_verilog/decode.v 2008/03/10.20:59:00 J.36
MO work/decode FL E:/potato_core/POTATO_TEST/cpu_verilog/decode.v
FL E:/potato_core/POTATO_TEST/cpu_verilog/forward.v 2008/03/11.14:21:42 J.36
MO work/forward FL E:/potato_core/POTATO_TEST/cpu_verilog/forward.v
FL E:/potato_core/POTATO_TEST/cpu_verilog/interrupt.v 2008/03/10.22:08:14 J.36
MO work/interrupt FL E:/potato_core/POTATO_TEST/cpu_verilog/interrupt.v
FL E:/potato_core/POTATO_TEST/cpu_verilog/mpu.v 2008/03/08.19:58:28 J.36
MO work/mpu FL E:/potato_core/POTATO_TEST/cpu_verilog/mpu.v
FL E:/potato_core/POTATO_TEST/cpu_verilog/pc_gen.v 2008/03/10.11:13:04 J.36
MO work/pc_gen FL E:/potato_core/POTATO_TEST/cpu_verilog/pc_gen.v
FL E:/potato_core/POTATO_TEST/cpu_verilog/regfile.v 2008/03/10.21:16:58 J.36
MO work/regfile FL E:/potato_core/POTATO_TEST/cpu_verilog/regfile.v
FL E:/potato_core/POTATO_TEST/cpu_verilog/reg_ex.v 2008/03/11.14:51:02 J.36
MO work/reg_ex FL E:/potato_core/POTATO_TEST/cpu_verilog/reg_ex.v
FL E:/potato_core/POTATO_TEST/cpu_verilog/reg_id.v 2008/03/10.22:22:24 J.36
MO work/reg_id FL E:/potato_core/POTATO_TEST/cpu_verilog/reg_id.v
FL E:/potato_core/POTATO_TEST/cpu_verilog/reg_if.v 2008/03/10.11:21:10 J.36
MO work/reg_if FL E:/potato_core/POTATO_TEST/cpu_verilog/reg_if.v
FL E:/potato_core/POTATO_TEST/cpu_verilog/reg_mem.v 2008/03/11.15:23:22 J.36
MO work/reg_mem FL E:/potato_core/POTATO_TEST/cpu_verilog/reg_mem.v
FL E:/potato_core/POTATO_TEST/cpu_verilog/write_back.v 2008/03/11.15:27:24 J.36
MO work/write_back FL E:/potato_core/POTATO_TEST/cpu_verilog/write_back.v
FL E:/potato_core/POTATO_TEST/TEST_CPU.tfw 2008/03/11.22:17:48 J.36
MO work/TEST_CPU FL E:/potato_core/POTATO_TEST/TEST_CPU.tfw MI cpu
FL $XILINX/verilog/src/glbl.v 2007/05/19.05:22:56 J.36
MO work/glbl FL $XILINX/verilog/src/glbl.v