hdllib.ref

32 risc cpu的参考设计

MO reg_mem NULL E:/potato_core/POTATO_TEST/cpu_verilog/reg_mem.v vlg50/reg__mem.bin 1205243422
MO wb_connect NULL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v vlg42/wb__connect.bin 1205245021
MO cntrl_rf NULL E:/potato_core/POTATO_TEST/cpu_verilog/cntrl_rf.v vlg3E/cntrl__rf.bin 1205243433
MO dcache_top NULL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v vlg6E/dcache__top.bin 1205245021
MO pc_gen NULL E:/potato_core/POTATO_TEST/cpu_verilog/pc_gen.v vlg3C/pc__gen.bin 1205243425
MO regfile NULL E:/potato_core/POTATO_TEST/cpu_verilog/regfile.v vlg72/regfile.bin 1205243421
MO reg_id NULL E:/potato_core/POTATO_TEST/cpu_verilog/reg_id.v vlg32/reg__id.bin 1205243424
MO reg_ex NULL E:/potato_core/POTATO_TEST/cpu_verilog/reg_ex.v vlg32/reg__ex.bin 1205243425
MO reg_if NULL E:/potato_core/POTATO_TEST/cpu_verilog/reg_if.v vlg34/reg__if.bin 1205243423
MO sdram_wbbus NULL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v vlg3D/sdram__wbbus.bin 1205245021
MO forward NULL E:/potato_core/POTATO_TEST/cpu_verilog/forward.v vlg15/forward.bin 1205243428
MO cpu NULL E:/potato_core/POTATO_TEST/cpu_verilog/cpu.v vlg50/cpu.bin 1205243435
MO TEST_CPU NULL E:/potato_core/POTATO_TEST/TEST_CPU.tfw vlg47/_t_e_s_t___c_p_u.bin 1205245101
MO icache NULL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v vlg65/icache.bin 1205245021
MO wb_arbiter NULL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v vlg11/wb__arbiter.bin 1205245021
MO dram NULL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v vlg48/dram.bin 1205245021
MO interrupt NULL E:/potato_core/POTATO_TEST/cpu_verilog/interrupt.v vlg29/interrupt.bin 1205243427
MO mpu NULL E:/potato_core/POTATO_TEST/cpu_verilog/mpu.v vlg4A/mpu.bin 1205243426
MO dcache NULL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v vlg5C/dcache.bin 1205245021
MO flash_wbbus NULL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v vlg4C/flash__wbbus.bin 1205245021
MO prom NULL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v vlg6A/prom.bin 1205245021
MO glbl NULL E:/Xilinx92i/verilog/src/glbl.v vlg2D/glbl.bin 1205243438
MO decode NULL E:/potato_core/POTATO_TEST/cpu_verilog/decode.v vlg50/decode.bin 1205243429
MO write_back NULL E:/potato_core/POTATO_TEST/cpu_verilog/write_back.v vlg33/write__back.bin 1205243420
MO addr_decoder NULL E:/potato_core/POTATO_TEST/cpu_verilog/dcache_top.v vlg5C/addr__decoder.bin 1205245021
MO alu NULL E:/potato_core/POTATO_TEST/cpu_verilog/alu.v vlg0A/alu.bin 1205243434