entity.cpp

5位的操作数X和Y输入后暂存在寄存器A和B中

////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /___/   /      
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////


#include "ieee/std_logic_unsigned/std_logic_unsigned.h"
#include "ieee/std_logic_arith/std_logic_arith.h"
#include "ieee/std_logic_1164/std_logic_1164.h"
#include "work/logic/entity.h"

static const char *entFileName = "C:/Users/Administrator/Desktop/disanci/logic.vhd";
#ifdef _MSC_VER
#pragma warning(disable: 4355)
#endif

Work_logic::Work_logic(const char *name, const char* ArchName, const char* fileName, int numOfLine): HSim__s6(false,name,"logic", ArchName, fileName, HSim::VhdlDesignEntity, numOfLine + 10)

{
  SE[0].initialize("cin1", &IeeeStd_logic_1164->Std_logic_vector, MKConstr(4, 0, HSim::DOWNTO), this, HSim::PortSigIn, (const char*)0);
  ;
  SE[0].setDefaultValue((char *)0);
;
  SE[1].initialize("cin2", &IeeeStd_logic_1164->Std_logic_vector, MKConstr(4, 0, HSim::DOWNTO), this, HSim::PortSigIn, (const char*)0);
  ;
  SE[1].setDefaultValue((char *)0);
;
  SE[2].initialize("cin3", &IeeeStd_logic_1164->Std_logic_vector, MKConstr(1, 0, HSim::DOWNTO), this, HSim::PortSigIn, (const char*)0);
  ;
  SE[2].setDefaultValue((char *)0);
;
  SE[3].initialize("clk", &IeeeStd_logic_1164->Std_logic, this, HSim::PortSigIn);
  ;
  SE[3].setDefaultValue((char *)0);
;
  SE[4].initialize("rst", &IeeeStd_logic_1164->Std_logic, this, HSim::PortSigIn);
  ;
  SE[4].setDefaultValue((char *)0);
;
  SE[5].initialize("cout", &IeeeStd_logic_1164->Std_logic_vector, MKConstr(4, 0, HSim::DOWNTO), this, HSim::PortSigOut, (const char*)0);
  ;
  SE[5].setDefaultValue((char *)0);
;
  SetPorts();
 
}

Work_logic::~Work_logic()
{
}

void Work_logic::SetPorts()
{
}

void Work_logic::constructEntityObject()
{
;
}