📄 entity.cpp
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////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ /
// \ \ \/
// \ \ Copyright (c) 2003-2004 Xilinx, Inc.
// / / All Right Reserved.
// /___/ /
// \ \ / \
// \___\/\___\
////////////////////////////////////////////////////////////////////////////////
#include "std/textio/textio.h"
#include "ieee/std_logic_textio/std_logic_textio.h"
#include "ieee/std_logic_unsigned/std_logic_unsigned.h"
#include "ieee/std_logic_arith/std_logic_arith.h"
#include "ieee/std_logic_1164/std_logic_1164.h"
#include "work/qwe/entity.h"
static const char *entFileName = "C:/Documents and Settings/Administrator/桌面/disanci/qwe.vhw";
#ifdef _MSC_VER
#pragma warning(disable: 4355)
#endif
Work_qwe::Work_qwe(const char *name, const char* ArchName, const char* fileName, int numOfLine): HSim__s6(false,name,"qwe", ArchName, fileName, HSim::VhdlDesignEntity, numOfLine + 6)
{
;
SetPorts();
}
Work_qwe::~Work_qwe()
{
}
void Work_qwe::SetPorts()
{
}
void Work_qwe::constructEntityObject()
{
;
}
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