ulaw_nl_l.vhd

使用VHDL语言

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity ulaw_nl_l is
	port(
			data			:in			std_logic;						--pcm signal a
			clock			:in			std_logic;						--clock signal
			framea		:in			std_logic;						--frame synchronous signal
			frameb		:in			std_logic;						--frame synchronous signal
			dataq			:out		std_logic_vector(13 downto 0));	--output overlap signal
end ulaw_nl_l;

architecture structure of ulaw_nl_l is
	COMPONENT s_p
		PORT(
			data			:in			std_logic;						--pcm signal a
			clock			:in			std_logic;						--clock signal
			frame			:in			std_logic;						--frame synchronous signal
			dataq			:out		std_logic_vector(7 downto 0));	--output overlap signal
	END COMPONENT;

	COMPONENT ulaw_s_invert
		PORT(
			data			:in			std_logic;						--pcm signal a
			dataq			:out			std_logic);						--output invert signal
	END COMPONENT;

--	COMPONENT ulaw_invert
--		PORT(
--			data			:in			std_logic_vector(7 downto 0);	--pcm signal a
--			frame			:in			std_logic;						--frame synchronous signal
--			dataq			:out		std_logic_vector(7 downto 0));	--output overlap signal
--	END COMPONENT;

	COMPONENT ulaw_8_14
		PORT(
			data			:in			std_logic_vector(7 downto 0);	--pcm signal a
			frame			:in			std_logic;						--frame synchronous signal
			dataq			:out			std_logic_vector(13 downto 0));	--output overlap signal
	END COMPONENT;
	
	signal	data_s_p		:std_logic_vector(7 downto 0);
--	signal	data_buf		:std_logic_vector(13 downto 0);
	signal  	data_invert	:std_logic;
begin
	u1:ulaw_s_invert
		port map(data	=> data,
				 dataq 	=> data_invert);
	u2:s_p
		port map(data	=> data_invert,
				 clock	=> clock,
				 frame	=> framea,
				 dataq	=> data_s_p);
	u3:ulaw_8_14
		port map(data	=> data_s_p,
				 frame	=> frameb,
				 dataq 	=> dataq);

--	dataq <= data_buf(13) & (not data_buf(12 downto 0) + '1') when data_buf(13) = '1' else
--				data_buf;

end structure;