s_p.vhd

来自「使用VHDL语言」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;

entity s_p is
		PORT(
			data			:in			std_logic;						--pcm signal a
			clock			:in			std_logic;						--clock signal
			frame			:in			std_logic;						--frame synchronous signal
			dataq			:out		std_logic_vector(7 downto 0));--output overlap signal
end s_p;

architecture rtl of s_p is
	signal data_in			:std_logic_vector(7 downto 0);
begin
	process(frame)
	begin	
		if frame'event and frame = '1' then
			dataq <= data_in;
		end if;
	end process;

	process (clock)
	begin
   		if clock'event and clock='1' then  
     		data_in <= data_in(6 downto 0) & data;
   		end if;
	end process;
end rtl;