ulaw_3.vhd

使用VHDL语言

library ieee;
use ieee.std_logic_1164.all;

entity ulaw_3 is
	port(
		rdata 		: in std_logic_vector(1 downto 0);
      rclock 		: in std_logic_vector(1 downto 0);
      rframe 		: in std_logic_vector(1 downto 0);
      tdata 			: out std_logic_vector(1 downto 0);
      tclock 		: in std_logic_vector(1 downto 0);
      tframe 		: in std_logic_vector(1 downto 0);

      rdata_loc 	: out std_logic;
      tdata_loc 	: in std_logic;
		frame_loc	: in std_logic;
		clock_loc	: in std_logic
		);
end ulaw_3;

architecture structure of ulaw_3 is

	component ulaw_nl_l
		port(
			data			:in			std_logic;						--pcm signal a
			clock			:in			std_logic;						--clock signal
			framea		:in			std_logic;						--serial convert to paralell's frame synchronous signal
			frameb		:in			std_logic;						--inversion and 8->13's frame synchronous signal
			dataq			:out			std_logic_vector(13 downto 0));	--output overlap signal
	end component;

	component ulaw_overlap
		port(
			dataa			:in			std_logic_vector(13 downto 0);	--pcm signal a
			datab			:in			std_logic_vector(13 downto 0);	--pcm signal b	
			frame			:in			std_logic;
			dataq			:out			std_logic_vector(13 downto 0));	--output overlap signal
	end component;

	component ulaw_l_nl
		port(
			data			:in			std_logic_vector(13 downto 0);	--pcm signal a
			clock			:in			std_logic;							--clock signal
			frame			:in			std_logic;							--frame synchronous signal
			dataq			:out			std_logic);						--output overlap signal
	end component;

   signal data_l_in1				 	:std_logic_vector(13 downto 0);
   signal data_l_in0				 	:std_logic_vector(13 downto 0);
   signal data_l_in_loc				:std_logic_vector(13 downto 0);

	signal data_l_o_in1				 :std_logic_vector(13 downto 0);
   signal data_l_o_in0				 :std_logic_vector(13 downto 0);
   signal data_l_o_in_loc			 :std_logic_vector(13 downto 0);
   signal 
   tmpframe : std_logic;
begin
--				tmpframe<=not tframe(1);	--v3.11
				tmpframe<= tframe(0); --v3.10
	u_ulaw_nl_l_0:ulaw_nl_l
		port map(data => rdata(0),
				 clock=> rclock(0),
				 framea=> rframe(0),
				 frameb=> rframe(0),
				 dataq => data_l_in0);	

	u_ulaw_nl_l_1:ulaw_nl_l
		port map(data => rdata(1),
				 clock=> rclock(1),
				 framea=> rframe(1),
				 frameb=> rframe(1),
				 dataq => data_l_in1);

	u_ulaw_nl_l_loc:ulaw_nl_l
		port map(data => tdata_loc,
				clock		=> clock_loc,
				framea	=> frame_loc,
				frameb	=> frame_loc,
				dataq => data_l_in_loc);	

   u_ulaw_overlap_0:ulaw_overlap
	   port map(
			dataa =>	data_l_in_loc,
			datab =>	data_l_in1,
			frame => tframe(0),
        	dataq => data_l_o_in0);

   u_ulaw_overlap_1:ulaw_overlap
	   port map(
			dataa =>	data_l_in0,
			datab =>	data_l_in_loc,
			frame => tmpframe,
        	dataq => data_l_o_in1);

   u_ulaw_overlap_3_loc:ulaw_overlap
	   port map(
			dataa =>	data_l_in0,
			datab =>	data_l_in1,
			frame	=> frame_loc,
        	dataq => data_l_o_in_loc);

	u_ulaw_l_nl_0:ulaw_l_nl
		port map(
			data	=> data_l_o_in0,
			clock	=> tclock(0),
			frame	=> tframe(0),
			dataq	=> tdata(0));

	u_ulaw_l_nl_1:ulaw_l_nl
		port map(
			data	=> data_l_o_in1,
			clock	=> tclock(1),
			frame	=> tframe(1),
			dataq	=> tdata(1));

	u_ulaw_l_nl_loc:ulaw_l_nl
		port map(
			data	=> data_l_o_in_loc,
			clock	=> clock_loc,
			frame	=> frame_loc,
			dataq	=> rdata_loc);
end structure;