ulaw_s_invert.vhd

使用VHDL语言

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ulaw_s_invert is
    Port ( data : in std_logic;
           dataq : out std_logic);
end ulaw_s_invert;

architecture Behavioral of ulaw_s_invert is

begin

   dataq <= not data;

end Behavioral;