ulaw_overlap.vhd

使用VHDL语言

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ulaw_overlap is
	port(
		dataa			:in			std_logic_vector(13 downto 0);		--pcm signal a
		datab			:in			std_logic_vector(13 downto 0);		--pcm signal b
		frame			:in			std_logic;									--frame synchronous signal
		dataq			:out		   std_logic_vector(13 downto 0));		--output overlap signal
end ulaw_overlap;

architecture rtl of ulaw_overlap is
	signal		sign			:std_logic;									--sign bit
	signal		xor_sign		:std_logic;									--xor sign bit
	signal		sel_sign		:std_logic;									--compare a and b
	signal		sel_code_a	:std_logic;									--select a or un_a
	signal		sel_code_b	:std_logic;									--select b or un_b
	signal		un_a			:std_logic_vector(12 downto 0);		--not a[n-2..0]
	signal		un_b			:std_logic_vector(12 downto 0);		--not b[n-2..0]
	signal		code_a		:std_logic_vector(12 downto 0);		--code_a[n-2..0]
	signal		code_b		:std_logic_vector(12 downto 0);		--code_b[n-2..0]
	signal		code_add		:std_logic_vector(12 downto 0);		--code_add[n-2..0]
	signal		code			:std_logic_vector(12 downto 0);		--code[n-2..0]
--	signal		overflow		:std_logic;									--overflow
	signal		integer_a	:integer	range 8191 downto 0;
	signal		integer_b	:integer	range 8191 downto 0;
	signal		code_tmp		:std_logic_vector(13 downto 0);
	signal		dataq_in	:std_logic_vector(13 downto 0);
begin
	integer_a <= conv_integer(dataa(12 downto 0));
	integer_b <= conv_integer(datab(12 downto 0));

	sign <=	dataa(13)	 		when	sel_sign = '0' else
				datab(13);

	xor_sign <= dataa(13) xor datab(13);

	sel_code_a <= xor_sign and sel_sign;
	sel_code_b <= xor_sign and (not sel_sign);

	un_a	<= not dataa(12 downto 0) + '1';
	un_b 	<= not datab(12 downto 0) + '1';
 
	code_a 	<= dataa(12 downto 0)		when	sel_code_a = '0' else un_a;
	code_b 	<= datab(12 downto 0)		when	sel_code_b = '0' else un_b;


	code_tmp <= ('0' & code_a) + ('0' & code_b) ;
	code_add <= code_tmp(12 downto 0);

	code <= code_add		when	code_tmp(13) = '0' or xor_sign = '1' else 
				"1111111111111";	 	
	sel_sign <= '1'			when	integer_a < integer_b else
					'0';

	dataq_in <= datab			when	dataa = "00000000000000" else
			 	sign & code;

	process(frame)
	begin
		if rising_edge(frame) then
			dataq	<=	dataq_in;
		end if;
	end process;

end rtl;