ulaw_l_nl.vhd

使用VHDL语言

library ieee;
use ieee.std_logic_1164.all;

entity ulaw_l_nl is
	port(
			data			:in			std_logic_vector(13 downto 0);--pcm linear signal
			clock			:in			std_logic;							--system clock
			frame			:in			std_logic;							--frame synchronous signal
			dataq			:out			std_logic);							--output overlap signal
end ulaw_l_nl;

architecture structure of ulaw_l_nl is
	COMPONENT ulaw_14_8
		PORT(
			data			:in			std_logic_vector(13 downto 0);	--linear signal 
			frame			:in			std_logic;								--frame synchronous signal
			dataq			:out			std_logic_vector(7 downto 0));	--output nolinear signal
	END COMPONENT;

	COMPONENT ulaw_s_invert
		PORT(
			data			:in			std_logic;	--pcm nolinear signal
			dataq			:out			std_logic);	--output inversion signal
	END COMPONENT;

	COMPONENT p_s
		PORT(
			data			:in			std_logic_vector(7 downto 0);	--pcm linear signal
			clock			:in			std_logic;							--clock signal
			frame			:in			std_logic;							--frame signal
			dataq			:out		std_logic);								--output overlap signal
	END COMPONENT;

	signal	data_p_s		:std_logic_vector(7 downto 0);
	signal	data_invert	:std_logic;
begin
	u1:ulaw_14_8
		port map(data	=> data,
				 frame	=> frame,
				 dataq 	=> data_p_s);
	u2:p_s
		port map(data	=> data_p_s,
				 clock	=> clock,
				 frame	=> frame,
				 dataq	=> data_invert);
	u3:ulaw_s_invert
		port map(data	=> data_invert,
				 dataq 	=> dataq);
end structure;