prev_cmp_ff.map.qmsg

QUARTUS II平台上的基于VHDL语言的电梯系统控制程序。

{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dr\[4\] lifttt.vhd(52) " "Info (10041): Inferred latch for \"dr\[4\]\" at lifttt.vhd(52)" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dr\[5\] lifttt.vhd(52) " "Info (10041): Inferred latch for \"dr\[5\]\" at lifttt.vhd(52)" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dr\[6\] lifttt.vhd(52) " "Info (10041): Inferred latch for \"dr\[6\]\" at lifttt.vhd(52)" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ur\[1\] lifttt.vhd(52) " "Info (10041): Inferred latch for \"ur\[1\]\" at lifttt.vhd(52)" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ur\[2\] lifttt.vhd(52) " "Info (10041): Inferred latch for \"ur\[2\]\" at lifttt.vhd(52)" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ur\[3\] lifttt.vhd(52) " "Info (10041): Inferred latch for \"ur\[3\]\" at lifttt.vhd(52)" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ur\[4\] lifttt.vhd(52) " "Info (10041): Inferred latch for \"ur\[4\]\" at lifttt.vhd(52)" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ur\[5\] lifttt.vhd(52) " "Info (10041): Inferred latch for \"ur\[5\]\" at lifttt.vhd(52)" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ur\[6\] lifttt.vhd(52) " "Info (10041): Inferred latch for \"ur\[6\]\" at lifttt.vhd(52)" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seg7dec seg7dec:inst4 " "Info: Elaborating entity \"seg7dec\" for hierarchy \"seg7dec:inst4\"" {  } { { "ff.bdf" "inst4" { Schematic "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/ff.bdf" { { 72 456 616 168 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "en seg7dec.vhd(17) " "Warning (10492): VHDL Process Statement warning at seg7dec.vhd(17): signal \"en\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seg7dec.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/seg7dec.vhd" 17 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "lift:inst2\|divide lift:inst2\|dir\[0\] " "Info: Duplicate register \"lift:inst2\|divide\" merged to single register \"lift:inst2\|dir\[0\]\"" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 26 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "lift:inst2\|ladd\[1\] " "Warning: Latch lift:inst2\|ladd\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA lift:inst2\|p3~0 " "Warning: Ports D and ENA on the latch are fed by the same signal lift:inst2\|p3~0" {  } {  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "lift:inst2\|ladd\[0\] " "Warning: Latch lift:inst2\|ladd\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA lift:inst2\|liftor\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal lift:inst2\|liftor\[2\]" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "run_wait\[3\] GND " "Warning (13410): Pin \"run_wait\[3\]\" stuck at GND" {  } { { "ff.bdf" "" { Schematic "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/ff.bdf" { { 32 416 592 48 "run_wait\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "120 " "Info: Implemented 120 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "19 " "Info: Implemented 19 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "94 " "Info: Implemented 94 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "152 " "Info: Allocated 152 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 14 12:12:18 2008 " "Info: Processing ended: Sun Dec 14 12:12:18 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}